Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

STMicroelectronics M24C16-DRMF3TG/K

Name: M24C16-DRMF3TG/K
Brand: STMicroelectronics
SKU: M24C16-DRMF3TG/K
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: M24C16-DRMF3TG/K

Manufacturer:: STMicroelectronics

Category:: Memory

Package:: 8-WFDFN Exposed Pad

Datasheet:: M24C16-DRMF3TG/K.pdf

Description:: IC EEPROM 16KBIT I2C 8MLP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:9,850

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

M24C16-DRMF3TG/K from STMicroelectronics is an AEC-Q100 Grade 1 automotive serial EEPROM with 16 Kbits (2 Kbytes) capacity, I²C interface supporting up to 1 MHz clock, 1.7–5.5 V supply, and operation from –40 °C to 125 °C. It features a 16-byte page size, embedded ECC for single-bit error correction, and a dedicated 16-byte identification page with permanent lock capability - used in engine control units for calibration storage.

For engineers reviewing the M24C16-DRMF3TG/K datasheet, M24C16-DRMF3TG/K pinout, M24C16-DRMF3TG/K application, or M24C16-DRMF3TG/K equivalent, key selection criteria include write endurance at 125 °C (600 k cycles), identification page locking behavior, Schmitt-trigger noise immunity on SDA/SCL, and WC pin-controlled hardware write protection across full memory array.

Technical Context

The M24C16-DRMF3TG/K implements a true EEPROM core with byte-alterable 2048 × 8-bit organization, internally segmented into 128 pages of 16 bytes each. Its I²C slave interface complies fully with standard, fast, and fast-plus modes (100 kHz / 400 kHz / 1 MHz), using open-drain SDA with mandatory external pull-up and edge-triggered SCL.

It integrates on-die charge pump and sequencer for write voltage generation, plus ECC logic that transparently corrects single-bit errors during read operations. The write control (WC) pin enables hardware-level memory lockdown independent of I²C commands, and the identification page supports both factory-coded device ID (00h–02h) and user-programmable parameters with irreversible lock via dedicated instruction.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	16 Kbits (2048 × 8 bits), organized as 128 pages × 16 bytes - enables efficient firmware parameter logging with minimal bus overhead per page write.
I²C speed	Up to 1 MHz - supports high-throughput calibration updates in real-time automotive diagnostics without requiring protocol translation.
Write endurance	600 k cycles at 125 °C - ensures reliable lifetime in under-hood ECU applications where thermal stress accelerates wear.
Data retention	50 years at 125 °C - guarantees integrity of safety-critical configuration data over full vehicle service life without refresh.
Supply range	1.7 V to 5.5 V - interoperable with 3.3 V and 5 V microcontrollers and tolerant of automotive battery transients.
Operating temp	–40 °C to +125 °C - qualified per AEC-Q100 Grade 1, validated for placement near powertrain and ADAS modules.
ESD rating	4000 V HBM - withstands handling and assembly stresses in automotive manufacturing environments.

Pinout & Package

Supplied in RoHS-compliant, halogen-free TSSOP8 (DW) package, 169 mil width, with exposed pad not connected. Pin 1 marked by notch or dot; lead finish is matte tin.

Pin/Terminal	Circuit Role	Design Meaning
1 (SDA)	Serial data bidirectional line	Open-drain I/O requiring external pull-up; supports wired-AND multi-slave bus topology and ACK/NACK signaling.
2 (V_SS)	Ground reference	Primary return path for internal charge pump and I/O drivers; must be low-impedance connection to system GND plane.
3 (SCL)	Serial clock input	CMOS-compatible input with Schmitt trigger; defines timing for data sampling and ACK window; no internal pull-up.
4 (WC)	Hardware write control	Active-high enable/disable for all write operations; floating or low = write enabled; high = full memory locked - immune to I²C command errors.
5–6 (NC)	No connect	Internally unconnected; must remain unconnected on PCB to avoid parasitic coupling or latch-up risk.
7 (V_CC)	Power supply	Accepts 1.7–5.5 V; requires local 10–100 nF ceramic decoupling capacitor placed within 2 mm of pin.
8 (NC)	No connect	Internally unconnected; must remain unconnected on PCB.

Key Features

Feature	Design Value
Embedded ECC x1	Single-bit error detection and correction per byte during read - eliminates need for external CRC checks in safety-critical boot parameter reads.
Dedicated ID page	16-byte page with factory ST ID (20h/E0h/0Bh) and user field; supports irreversible lock to prevent tampering with calibration or security keys.
Page write time	≤4 ms for up to 16 bytes - enables atomic update of related parameters (e.g., throttle map + timing offset) without intermediate invalid states.
Schmitt-trigger inputs	On SDA and SCL - rejects bus noise up to 30% V_CC, eliminating external filtering components in noisy engine bay wiring harnesses.
Write cycle polling	ACK-based polling protocol - allows host MCU to minimize wait time without fixed delays or timer interrupts, improving real-time responsiveness.

Applications

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing adaptive fuel trim values, knock sensor learning offsets, and cold-start enrichment tables updated during vehicle operation.

IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed 50-year retention at 125 °C and ECC-protected reads during power-on self-test.

Use Value: Eliminates recalibration after battery disconnect and prevents corruption of emission-critical maps due to bit flips in high-temp environments.

Use Scenario: Holding camera calibration coefficients, radar object classification thresholds, and lane-departure warning hysteresis settings.

IC Role / Device Role / Timing Role: Secure, write-protected configuration store accessed via I²C during boot and runtime reconfiguration.

Use Value: Enables field-upgradable ADAS behavior without exposing sensitive tuning data to unauthorized writes via WC pin hardware lock.

Body Control Module (BCM)

Electric Power Steering (EPS)

Use Scenario: Retaining seat/mirror position memory, door lock programming, and lighting fade profiles across ignition cycles.

IC Role / Device Role / Timing Role: Low-power, high-reliability EEPROM interfaced to 3.3 V microcontroller with 1 MHz I²C burst writes during setup.

Use Value: Supports >100,000 seat-position adjustments over vehicle lifetime while maintaining data integrity through repeated thermal cycling.

Use Scenario: Storing torque sensor zero-point compensation, motor phase alignment offsets, and assist-map scaling factors.

IC Role / Device Role / Timing Role: Safety-relevant nonvolatile storage with AEC-Q100 Grade 1 qualification and hardware write lock (WC) to prevent accidental overwrite during CAN fault recovery.

Use Value: Ensures steering assist remains consistent after ECU reset and meets ASIL-B data integrity requirements via ECC and locked ID page.

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT24C16D-SSHM-T	16 Kbit I²C EEPROM, AEC-Q100 Grade 2 (–40 °C to 105 °C), no identification page or ECC, max 400 kHz clock.	Limited to cabin modules; unsuitable for under-hood use above 105 °C or safety-critical ECC-required functions.	Select only for cost-sensitive interior applications where temperature and reliability demands are lower.
BR24G16NUX-5TR	16 Kbit I²C EEPROM, AEC-Q100 Grade 1, 1.7–5.5 V, but no WC pin or identification page; supports 1 MHz but lacks ECC.	Acceptable for basic parameter storage in transmission control, but cannot replace M24C16's secure ID page or ECC-protected reads.	Choose when hardware write lock and ECC are not required, and board space favors smaller DFN package.

Compared with AT24C16D-SSHM-T and BR24G16NUX-5TR, the M24C16-DRMF3TG/K uniquely combines Grade 1 temperature rating, integrated ECC, hardware WC lock, and programmable/lockable ID page - making it the only option for ASIL-B–aligned powertrain and ADAS calibration storage where data integrity and tamper resistance are mandatory.

Availability

M24C16-DRMF3TG/K is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, body control modules, and electric power steering systems requiring stable component supply across extended automotive lifecycles.

Supply support for M24C16-DRMF3TG/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

The M24C16-DRMF3TG/K belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical nonvolatile storage in harsh-temperature ECUs where data integrity, long-term retention, and hardware-level write protection are essential.

FAQ

What is the function of the WC pin, and how does it interact with I²C write commands?

The WC (Write Control) pin is an active-high hardware lock that disables all write operations to the entire memory array when driven high - regardless of I²C address or data sent. When WC = high, the device acknowledges device select and address bytes but returns NACK on data bytes, preventing any memory modification. This provides fail-safe protection against firmware bugs or bus glitches that could corrupt calibration data.

Does the M24C16-DRMF3TG/K support standard, fast, and fast-plus I²C modes?

Yes - it fully supports standard mode (100 kHz), fast mode (400 kHz), and fast-plus mode (1 MHz) I²C protocols. Its SDA and SCL inputs include Schmitt triggers and level-shifted buffers compatible with 1.7–5.5 V V_CC, enabling direct interface with both 3.3 V and 5 V microcontrollers without external level shifters.

How is the identification page structured, and what happens when it is locked?

The identification page is a dedicated 16-byte area containing ST's 3-byte device ID (20h/E0h/0Bh) followed by 13 user-programmable bytes. Once locked via the "Lock Identification Page" instruction, all subsequent write attempts to this page return NACK, and read operations continue normally - ensuring calibration keys or security tokens remain immutable while preserving read access for verification.

Can the M24C16-DRMF3TG/K be used in systems requiring ASIL-B compliance?

While the device itself is not ASIL-certified, its AEC-Q100 Grade 1 qualification, 50-year data retention at 125 °C, embedded ECC for single-bit error correction, and hardware WC pin make it suitable for inclusion in ASIL-B–compliant systems - provided system-level fault tolerance (e.g., checksum validation, dual-storage redundancy) is implemented per ISO 26262 requirements.

M24C16-DRMF3TG/K Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-WFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 16Kbit

Memory Organization:: 2K x 8

Memory Interface:: I2C

Clock Frequency:: 1 MHz

Write Cycle Time - Word, Page:: 4ms

Access Time:: 450 ns

Voltage - Supply:: 1.7V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-MLP (2x3)

M24C16-DRMF3TG/K FAQ

1.How can I place an order for M24C16-DRMF3TG/K through Aetrix?

Please submit a Request for Quotation (RFQ) for M24C16-DRMF3TG/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M24C16-DRMF3TG/K reliable?

The price and inventory of M24C16-DRMF3TG/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M24C16-DRMF3TG/K is usually 5 days.

3.What payment methods are accepted for M24C16-DRMF3TG/K?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M24C16-DRMF3TG/K transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M24C16-DRMF3TG/K?

M24C16-DRMF3TG/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M24C16-DRMF3TG/K order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M24C16-DRMF3TG/K?

For technical support, including M24C16-DRMF3TG/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M24C16-DRMF3TG/K requirements.

6.How does Aetrix verify that M24C16-DRMF3TG/K is sourced from the original manufacturer or authorized distributors?

All M24C16-DRMF3TG/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M24C16-DRMF3TG/K meets industry standards.

7.What is the process for return or replacement of M24C16-DRMF3TG/K?

All M24C16-DRMF3TG/K units undergo pre-shipment inspection (PSI). If there is an issue with M24C16-DRMF3TG/K, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M24C16-DRMF3TG/K part is unused and in its original packaging.

Return procedure for M24C16-DRMF3TG/K:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…