STMicroelectronics M27C256B-12C6
- Part No.:
- M27C256B-12C6
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
M27C256B-12C6.pdf
- Description:
- IC EPROM 256KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:2,414
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M27C256B-12C6 from STMicroelectronics is a 256 Kbit (32K × 8) UV-erasable EPROM with 45 ns access time, 5V ±10% supply, and 12.75V programming voltage. It features dual-line output control (E/G), electronic signature (20h/8Dh), and operates across –40°C to 85°C. Used in legacy microprocessor boot memory, industrial controller firmware storage, and embedded system configuration tables.
For engineers reviewing the M27C256B-12C6 datasheet, M27C256B-12C6 pinout, M27C256B-12C6 application, or M27C256B-12C6 equivalent, key selection criteria include UV-erase capability, TTL-compatible timing, two-line enable architecture for bus contention avoidance, and FDIP28W package compatibility with EPROM programmers.
Technical Context
The M27C256B-12C6 implements a standard NMOS EPROM cell array with address decoding logic supporting A0–A14 (15-bit address space) and Q0–Q7 (8-bit parallel data bus). Its two-line control architecture separates chip selection (E) from output gating (G), enabling low-power standby (100 µA) and eliminating bus contention in multi-device memory systems.
Programming requires VPP = 12.75V ±0.25V, VCC = 6.25V ±0.25V, and 100 µs pulse width per word, with automatic margin verification via PRESTO II algorithm. Electronic signature mode uses A9 = 12V to read manufacturer code (20h) and device code (8Dh) on Q7–Q0.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 256 Kbit (32,768 × 8), fixed organization - no bank switching or variable addressing modes. |
| Access Time | 45 ns (tAVQV) at 5V - defines maximum clock rate for synchronous read cycles in 8086/8088-based systems. |
| Supply Voltage | 5V ±10% in read mode - compatible with legacy TTL/CMOS logic rails without regulation overhead. |
| Programming Voltage | VPP = 12.75V ±0.25V - requires dedicated EPROM programmer; not supported by standard microcontroller GPIO. |
| Standby Current | 100 µA at CMOS E high - enables power-sensitive applications where memory remains powered but inactive. |
| Operating Temp | –40°C to +85°C - validated for industrial control environments, not extended automotive or military ranges. |
| Electronic Signature | Manufacturer Code 20h, Device Code 8Dh - used by programmers to auto-select correct algorithm and verify part identity pre-programming. |
Pinout & Package
Package: FDIP28W (28-pin ceramic frit-seal DIP with UV-transparent window). Designed for UV erasure under 2537 Å light for 15–20 minutes at ≥15 W·sec/cm² dose.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address Inputs | 15-bit address bus; latched internally on E low transition - supports full 32K-word decode without external latch. |
| Q0–Q7 | Data Outputs | Bi-directional during programming (data-in), output-only during read - requires external pull-ups only if driving long traces. |
| E | Chip Enable | Primary device select; TTL/CMOS-compatible active-low - places device in standby (100 µA) when high. |
| G | Output Enable | Secondary output gate; active-low - controls Q0–Q7 Hi-Z state independently of E, enabling shared bus arbitration. |
| VPP | Programming Supply | 12.75V input required only during programming/verify - must be applied after VCC and removed before VCC. |
| VCC | Supply Voltage | 5V ±10% for read; 6.25V ±0.25V for programming - dual-voltage operation mandates separate power sequencing control. |
| VSS | Ground | Signal reference for all inputs/outputs - requires dedicated low-inductance 0.1 µF ceramic decoupling per device. |
| A9 (ES) | Electronic Signature Control | 12V input (11.5–12.5V) activates signature mode - not used in normal read/program; must be isolated during standard operation. |
Key Features
| Feature | Design Value |
|---|---|
| Two-line output control (E + G) | Eliminates bus contention in multi-chip memory arrays by decoupling device selection from output drive timing. |
| UV erasure via FDIP28W window | Enables field reprogramming using standard 2537 Å UV lamps - no electrical erase circuitry required. |
| PRESTO II programming algorithm | Guarantees cell margin with 100 µs pulses and automatic verify; no over-programming needed. |
| Electronic signature (20h/8Dh) | Allows automated programmer identification and algorithm matching - prevents incorrect programming sequences. |
| Low standby current (100 µA) | Reduces system-level quiescent power in always-on embedded controllers without requiring power cycling. |
Applications
| Industrial PLC Firmware Storage | Legacy PC BIOS Boot ROM |
|---|---|
|
Use Scenario: Storing ladder logic firmware in programmable logic controllers operating in factory-floor environments with wide temperature swings and EMI. IC Role / Device Role / Timing Role: Nonvolatile boot memory holding initialization code executed at power-up; accessed via 80C188EB address/data bus with 45 ns tAVQV timing constraint. Use Value: UV-erasability allows firmware updates during maintenance windows without board replacement; FDIP28W package withstands industrial handling and cleaning solvents. |
Use Scenario: Holding POST routines and hardware initialization code in early x86 motherboards (e.g., 286/386 systems) where BIOS size fits within 256 Kbit. IC Role / Device Role / Timing Role: Primary boot ROM mapped to 0xE0000–0xFFFFF; timing-critical reads synchronized to 8 MHz ISA bus clocks using E/G handshaking. Use Value: 45 ns access time meets 80286/386 minimum instruction fetch requirements; electronic signature prevents accidental programming of incompatible EPROMs. |
| Avionics Configuration Memory | Medical Device Calibration Table Storage |
|
Use Scenario: Storing flight control parameter tables in certified avionics units where data integrity must survive 10+ years without refresh. IC Role / Device Role / Timing Role: Read-only configuration store accessed during pre-flight self-test; verified via checksum against redundant EEPROM copy. Use Value: Ceramic FDIP28W package provides hermetic sealing and radiation tolerance; UV erasure enables post-certification field updates under engineering change control. |
Use Scenario: Holding sensor calibration coefficients and safety-critical lookup tables in Class II medical instruments (e.g., infusion pumps) requiring traceable firmware history. IC Role / Device Role / Timing Role: Static memory mapped to microcontroller's external bus; read during power-on self-test before actuator enable. Use Value: 100 µA standby current extends battery life in portable devices; electronic signature ensures only approved calibration files are loaded during service. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM27C256B-12DC | Same 256 Kbit × 8 organization, 45 ns access, but uses PDIP28 (no UV window); requires one-time programming only. | Used where field reprogramming is unnecessary and cost sensitivity favors plastic over ceramic packaging. | Select when UV erasure is not required and RoHS compliance (Pb-free PDIP) is mandatory. |
| MX27C256-12PC | Pin-compatible 256 Kbit EPROM with identical AC/DC specs, but manufactured by Macronix; electronic signature codes differ (1Ch/8Dh). | Drop-in replacement in existing designs where STMicroelectronics supply continuity is constrained. | Verify programmer support for Macronix signature codes before deployment; same FDIP28W mechanical fit. |
Compared with AM27C256B-12DC, M27C256B-12C6 enables field firmware updates via UV erasure, while MX27C256-12PC offers second-source availability with identical timing but distinct signature verification logic.
Availability
M27C256B-12C6 is available at Aetrix Electronics and suitable for industrial PLC firmware storage, legacy x86 BIOS boot ROMs, and avionics configuration memory requiring stable component supply across extended product lifecycles.
Supply support for M27C256B-12C6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in analog, MCU, power, and memory solutions for industrial, automotive, and consumer markets.
The M27C256B belongs to ST's legacy EPROM product line, designed specifically for reliable, field-erasable nonvolatile storage in microprocessor-based systems where firmware update flexibility outweighs density or speed limitations.
FAQ
What UV wavelength and exposure time are required to fully erase M27C256B-12C6?
Full erasure requires exposure to 2537 Å short-wave ultraviolet light at ≥15 W·sec/cm² integrated dose. Using a standard 12,000 µW/cm² UV lamp, place the FDIP28W package within 2.5 cm of the lamp for 15–20 minutes. Room fluorescent lighting may cause partial erasure over 3 years; direct sunlight can erase in ~1 week.
Can M27C256B-12C6 be programmed with a modern USB EPROM programmer?
Yes, provided the programmer supports 12.75V VPP, 6.25V VCC, PRESTO II algorithm, and M27C256B-specific electronic signature (20h/8Dh). Verify compatibility with the programmer's device database - generic "27C256" support may not include ST's margin-verify sequence or A9 voltage activation for signature read.
Is the FDIP28W package RoHS-compliant?
No. The FDIP28W package contains leaded solder in its ceramic-to-metal seal and is exempt from RoHS under Annex III (category 7a - high-melting temperature type solders). STMicroelectronics discontinued RoHS-compliant replacements; PDIP28 (AM27C256B) is the RoHS alternative but lacks UV erasure capability.
How does the two-line control (E and G) prevent bus contention in multi-EPROM systems?
E (Chip Enable) places deselected devices in 100 µA standby with outputs in Hi-Z, while G (Output Enable) gates Q0–Q7 independently. This allows one EPROM to drive the bus (E low + G low) while others remain powered but electrically isolated (E high → Hi-Z regardless of G state), eliminating signal collisions during read bursts.
M27C256B-12C6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EPROM
- Technology:
- EPROM - OTP
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- -
- Access Time:
- 120 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (11.35x13.89)
M27C256B-12C6 FAQ
1.How can I place an order for M27C256B-12C6 through Aetrix?
Please submit a Request for Quotation (RFQ) for M27C256B-12C6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M27C256B-12C6 reliable?
The price and inventory of M27C256B-12C6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M27C256B-12C6 is usually 5 days.
3.What payment methods are accepted for M27C256B-12C6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M27C256B-12C6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M27C256B-12C6?
M27C256B-12C6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M27C256B-12C6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M27C256B-12C6?
For technical support, including M27C256B-12C6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M27C256B-12C6 requirements.
6.How does Aetrix verify that M27C256B-12C6 is sourced from the original manufacturer or authorized distributors?
All M27C256B-12C6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M27C256B-12C6 meets industry standards.
7.What is the process for return or replacement of M27C256B-12C6?
All M27C256B-12C6 units undergo pre-shipment inspection (PSI). If there is an issue with M27C256B-12C6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M27C256B-12C6 part is unused and in its original packaging.
Return procedure for M27C256B-12C6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M27C256B-12C6 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

