Renesas M37151EFFP#U0

Overview

M37151EFFP from Mitsubishi Electric is an 8-bit single-chip CMOS microcomputer with integrated closed caption data slicer, on-screen display (OSD) controller, and electrically programmable PROM. It delivers 60 KB ROM, 2048 bytes RAM, 6× 8-bit timers, 8-channel 7-bit A-D comparator, and 5× 8-bit PWM outputs - enabling real-time caption decoding and character-based video overlay in analog TV systems.

For engineers reviewing the M37151EFFP datasheet, M37151EFFP pinout, M37151EFFP application, or M37151EFFP equivalent, this device supports precise timing-critical OSD positioning (128×512 pixel grid), multi-master I²C-BUS (3 channels), and hardware-accelerated data slicing for NTSC/PAL closed caption signals - critical for legacy broadcast receiver design and retrofit OSD upgrades.

Technical Context

The M37151EFFP integrates a 740-family CPU core with 71 basic instructions and 0.5 µs minimum instruction execution time at 8 MHz. Its memory architecture includes dedicated OSD RAM (128 bytes), OSD ROM (10 KB), and ROM correction memory for field-programmable firmware patches.

Hardware peripherals are tightly coupled to video timing: P50/P51 accept HSYNC/VSYNC inputs; P52–P55 output RGB+OUT video signals; CVIN, VHOLD, HLF, and FILT pins interface directly with composite video and data slicer circuitry; and the built-in data slicer supports CC mode (16×26 dot character area) and OSD mode (16×20 dot, 8 font sizes, 8 colors per character).

Key Specifications

Pinout & Package

42-pin plastic SSOP (Outline 42P2R), 0.65 mm pitch, surface-mount package. Pin functions validated per Mitsubishi datasheet Rev. 1.0, Figures 4.1 and Table 7.1–7.2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar closed caption and OSD controller applications.

Compared with MB89950 and UPD78F0513, the M37151EFFP uniquely combines OTP PROM, hardware caption slicing, and direct RGB+OUT video outputs - delivering lowest component count and fastest time-to-market for analog TV OSD integration.

Availability

M37151EFFP is available at Aetrix Electronics and suitable for analog TV manufacturing, broadcast equipment refurbishment, and professional video monitor upgrade programs requiring stable component supply and long-term obsolescence mitigation.

Supply support for M37151EFFP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Mitsubishi Electric Corporation is a Japanese multinational specializing in power systems, industrial automation, and semiconductor solutions for automotive, industrial, and consumer electronics markets.

The M37151 series was designed specifically for cost-sensitive analog video applications requiring integrated closed caption decoding and on-screen display - targeting TV manufacturers needing single-chip solutions before the digital transition.

FAQ

What is the maximum character display capacity of the M37151EFFP in OSD mode?

The M37151EFFP supports 32 characters × 2 lines as standard in OSD mode, with software extension enabling ≥3 lines. Each character uses a 16×20 dot matrix, and the device provides 254 predefined glyphs stored in internal OSD ROM. The M37151EFFP also supports per-character coloring (8 colors), background fill, and attributes like border and smooth roll-up - all managed by dedicated hardware without CPU intervention.

Does the M37151EFFP require external components to implement closed caption decoding?

Yes - the M37151EFFP requires external passive components for proper closed caption operation: a coupling capacitor on CVIN, a hold capacitor between VHOLD and VSS, an RC filter between HLF and VSS, and a capacitor between FILT and VSS. These form the analog front-end for the internal data slicer. No external decoder IC or digital logic is needed - the M37151EFFP performs full EIA-608 extraction and formatting internally.

Can the M37151EFFP be reprogrammed after soldering to the PCB?

No - the M37151EFFP contains a one-time programmable (OTP) PROM, as confirmed in Section 17 of the datasheet ("ONE TIME PROM VERSION M37151EFFP MARKING"). Firmware must be verified and burned prior to assembly. This differs from Flash-based MCUs and ensures immunity to accidental overwrite in the field, making it suitable for fixed-function broadcast applications where firmware stability is critical.

What video timing signals does the M37151EFFP accept for OSD synchronization?

The M37151EFFP accepts HSYNC on P50 and VSYNC on P51 to lock its on-screen display rendering to the incoming analog video signal. These inputs support standard NTSC (525-line) and PAL (625-line) timing. The M37151EFFP uses these signals to calculate exact pixel positions - enabling precise horizontal (128-level) and vertical (512-level) placement of characters and windows without external timing generators.

How many independent I²C-BUS interfaces does the M37151EFFP support?

The M37151EFFP supports three independent multi-master I²C-BUS interfaces: Channel 1 (P11/SCL1 and P13/SDA1), Channel 2 (P12/SCL2 and P14/SDA2), and Channel 3 (P31/SCL3 and P30/SDA3). Each channel uses N-channel open-drain drivers compatible with standard I²C voltage levels and supports arbitration, clock stretching, and repeated START conditions - allowing concurrent communication with tuner modules, EEPROMs, and remote control receivers.