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Renesas M66591GP#RB1S
- Part No.:
- M66591GP#RB1S
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
M66591GP#RB1S.pdf
- Description:
- MCU LQFP
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Product details
Overview
M66591GP#RB1S from Renesas Electronics is a USB 2.0 peripheral controller IC compliant with USB Specification Revision 2.0, supporting both Hi-Speed (480 Mbps) and Full-Speed (12 Mbps) operation. It integrates a USB transceiver, hardware protocol engine for bit stuffing, CRC, NRZI, and packet detection, and provides up to 7 configurable endpoints with a total 3.5 KB FIFO. It is used in digital cameras, printers, and external storage devices requiring high-bandwidth USB peripheral connectivity.
For engineers reviewing the M66591GP#RB1S datasheet, M66591GP#RB1S pinout, M66591GP#RB1S application, or M66591GP#RB1S equivalent, key selection considerations include Hi-Speed/Full-Speed dual-mode support, 80-pin LQFP package with separate/multiplex CPU bus and split DMA interface, 12/24/48 MHz clock input flexibility, and 1.8V/3.3V I/O voltage compatibility.
Technical Context
The M66591GP#RB1S implements a full hardware USB protocol stack - including CRC generation/checking, NRZI encoding/decoding, bit stuffing, and address filtering - offloading host CPU processing. Its Serial Interface Engine (SIE) side block contains the USB transceiver (UTM), protocol engine (Prtcl_Eng), PIPE controller, and interrupt controller, operating independently from the CPU-side register and FIFO blocks.
It supports three bus configurations: 16-bit separate, 16-bit multiplex, and 8-bit split DMA interface, enabling flexible integration into embedded systems with varying bandwidth and resource constraints. Endpoint configuration (PIPE0–PIPE6) allows per-channel selection of transfer type (control/bulk/interrupt), buffer size (64–512 bytes), and buffering mode (single/double/continuous).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| USB Compliance | USB 2.0 specification revision 2.0 compliant - supports all mandatory transfer types (control, bulk, interrupt) and electrical signaling requirements for Hi-Speed and Full-Speed modes. |
| Data Rate | Hi-Speed: 480 Mbps; Full-Speed: 12 Mbps - enables high-throughput peripheral data transfer while maintaining backward compatibility with legacy USB hosts. |
| FIFO Capacity | 3.5 KB total endpoint FIFO - distributed across up to 7 endpoints (PIPE0–PIPE6), with configurable allocation (e.g., 512-byte double-buffered for PIPE1–PIPE2). |
| Clock Input | 12 / 24 / 48 MHz crystal or external clock - selectable via Xtal[1:0] bits; PLL-based internal clock generation supports Hi-Speed timing accuracy. |
| Bus Interface | 16-bit separate/multiplex CPU interface + 8-bit split DMA interface - decouples data movement from CPU cycles, enabling efficient large-data transfers without CPU overhead. |
| I/O Voltage | 1.8 V or 3.3 V VIF supply - supports low-power SoC integration and mixed-voltage system design with level-shifting flexibility. |
| Package | 80-pin LQFP (80P6R-A), 0.4 mm pitch - surface-mount compatible with standard PCB assembly processes and thermal management for industrial peripheral applications. |
Pinout & Package
Package: 80-pin LQFP (80P6R-A), 0.4 mm pitch, body size 12 mm × 12 mm, exposed pad not specified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D15–D8 | Data Bus (MSB) | 8-bit bidirectional data path for 16-bit CPU interface; used as D15–D8 in separate or multiplex mode. |
| D7/AD7–D1/AD1, D0 | Data/Address Bus (LSB) | In multiplex mode: time-shared AD7–AD1 address inputs + D7–D0 data; in separate mode: D7–D0 only. |
| A7/ALE, A6–A1 | Address Bus / Latch Enable | A7 functions as ALE in multiplex mode; A6–A1 unused in multiplex mode; all used as address lines in separate mode. |
| SD7/PA7–SD0/PA0 | Split Bus / GPIO | Selectable between 8-bit DMA split bus interface or general-purpose I/O port (PA0–PA7) via DB_Cfg bit. |
| DHP / DHM | USB Hi-Speed Differential Pair | Direct connection to USB 480 Mbps D+ and D− lines; requires proper impedance-controlled routing and ESD protection. |
| DFP / DFM | USB Full-Speed Differential Pair | Connected internally to DHP/DHM via 43 Ω resistors; used when operating in Full-Speed mode only. |
| TR_ON / RPU | USB Pull-up Power & Control | TR_ON outputs regulated 3.3 V for D+ pull-up; RPU connects TR_ON to D+ via 1.5 kΩ resistor to signal device speed during enumeration. |
| CONF_ON / SUSP_ON | USB Status Outputs | N-channel open-drain signals indicating configured state (CONF_ON) and suspend state (SUSP_ON); require external pull-ups. |
| XIN / XOUT | Crystal Oscillator Interface | Connects to 12/24/48 MHz crystal; XIN accepts external clock if XOUT left open - critical for USB timing stability. |
| RST_N | Active-Low Reset | Asynchronous hardware reset; initializes all registers and internal state; must be held low ≥10 ms after power stabilization. |
Key Features
| Feature | Design Value |
|---|---|
| Hardware USB Protocol Engine | Offloads CRC generation/checking, NRZI encoding/decoding, bit stuffing, and packet parsing - eliminates firmware overhead for USB link-layer operations. |
| Configurable Endpoint Architecture | 7 independent PIPEs (PIPE0–PIPE6) with per-endpoint FIFO sizing (64–512 B), buffering mode (single/double/continuous), and transfer type assignment. |
| Dual-Mode USB Transceiver | Integrated analog front-end supports automatic Hi-Speed/Full-Speed detection and mode switching - no external transceiver required. |
| Independent DMA Interface | 8-bit split bus (SD0–SD7) operates independently of CPU bus - enables concurrent data streaming and CPU processing for real-time peripherals. |
| Flexible Clock & Power Options | Supports 12/24/48 MHz input with internal PLL; separate 1.8 V/3.3 V I/O supply (VIF) and 3.3 V core/analog supplies - simplifies power domain partitioning. |
Applications
| High-Resolution Digital Camera | USB 2.0 External Hard Drive |
|---|---|
|
Use Scenario: High-speed image burst transfer from CMOS sensor to host PC via USB cable. IC Role / Device Role / Timing Role: USB peripheral controller managing Hi-Speed bulk transfers, endpoint buffering, and USB protocol compliance. Use Value: 480 Mbps throughput enables sub-second transfer of 12 MP JPEG files; 3.5 KB FIFO absorbs sensor-to-USB latency jitter without CPU intervention. |
Use Scenario: Mass storage class (MSC) interface between SATA SSD and USB host. IC Role / Device Role / Timing Role: USB device controller implementing BOT (Bulk-Only Transport) protocol with dual-buffered bulk endpoints. Use Value: 512-byte double-buffered PIPE1/PIPE2 supports sustained 35 MB/s read/write; hardware CRC ensures data integrity during high-volume transfers. |
| Multi-Function Printer (MFP) | Industrial USB Data Acquisition Module |
|
Use Scenario: Simultaneous USB printing, scanning, and firmware update over single USB connection. IC Role / Device Role / Timing Role: Multi-interface USB peripheral handling control (PIPE0), bulk (PIPE1–PIPE4), and interrupt (PIPE5–PIPE6) transfers. Use Value: 7 endpoint support enables concurrent printer command channel, scanner image stream, and HID-style update interface without bandwidth contention. |
Use Scenario: Real-time sensor data streaming (e.g., 16-bit ADC samples at 100 kSPS) to host PC for analysis. IC Role / Device Role / Timing Role: USB peripheral controller with continuous-transfer-mode PIPE0 and DMA-driven data ingestion. Use Value: Split bus (SD0–SD7) + DREQ/DACK handshake enables zero-CPU-load streaming; 48 MHz clock input ensures precise sample timing alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB 2.0 peripheral controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISP1583 (NXP) | Single-chip USB 2.0 transceiver + PHY; 32 KB integrated RAM; supports OTG but lacks split DMA interface. | Better suited for host/peripheral dual-role designs; higher memory reduces external SRAM need but increases BOM cost. | Select ISP1583 when OTG capability or larger on-chip buffer is prioritized over deterministic DMA streaming performance. |
| SL811HS (Cypress) | Legacy USB 2.0 peripheral controller; 2 KB FIFO; supports only 12/48 MHz clocks; no Hi-Speed auto-detection logic. | Limited to simpler, lower-bandwidth peripherals; requires more firmware intervention for speed negotiation and error recovery. | Choose SL811HS only for cost-sensitive, non-Hi-Speed applications where design reuse or legacy driver support is critical. |
Compared with ISP1583 and SL811HS, the M66591GP#RB1S delivers superior deterministic data throughput via its dedicated split DMA interface and hardware-accelerated protocol engine - making it optimal for real-time, high-bandwidth USB peripherals where CPU offload and timing predictability are essential.
Availability
M66591GP#RB1S is available at Aetrix Electronics and suitable for digital camera modules, industrial data loggers, and USB-connected storage subsystems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for M66591GP#RB1S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor manufacturer specializing in microcontrollers, analog, and mixed-signal solutions for automotive, industrial, and consumer applications.
The M66591GP#RB1S belongs to Renesas' ASSP (Application-Specific Standard Product) USB controller family, designed specifically to enable high-performance, low-software-overhead USB 2.0 peripheral functionality in resource-constrained embedded systems.
FAQ
What USB speeds does the M66591GP#RB1S support?
The M66591GP#RB1S supports both Hi-Speed (480 Mbps) and Full-Speed (12 Mbps) USB 2.0 operation. Hardware-based speed detection and mode switching allow automatic negotiation with the host; Hi-Speed mode is enabled via the HSE bit in USB Transceiver Control Register 0. The M66591GP#RB1S does not support Low-Speed mode.
How many endpoints does the M66591GP#RB1S support, and how is FIFO allocated?
The M66591GP#RB1S supports up to 7 endpoints (PIPE0–PIPE6), with a total 3.5 KB shared FIFO memory. Allocation is configurable per PIPE: PIPE0 uses 256 bytes for control transfers; PIPE1–PIPE4 support 512-byte buffers (double- or single-buffered); PIPE5–PIPE6 use 64-byte buffers for interrupt transfers. The M66591GP#RB1S allows dynamic reconfiguration via register writes.
Does the M66591GP#RB1S require an external USB transceiver?
No, the M66591GP#RB1S integrates a complete USB 2.0 transceiver - including analog front-end, differential receivers/transmitters, and pull-up control circuitry. DHP/DHM pins connect directly to the USB D+/D− lines; DFP/DFM pins are internally routed and require external 43 Ω resistors only in Full-Speed mode. No external transceiver IC is needed for either Hi-Speed or Full-Speed operation.
What bus interfaces does the M66591GP#RB1S provide for CPU and DMA connectivity?
The M66591GP#RB1S offers three interface options: a 16-bit separate CPU bus, a 16-bit multiplexed CPU bus (with ALE strobe), and an independent 8-bit split DMA bus (SD0–SD7). The MPBUS pin selects between separate/multiplex modes; the split bus operates asynchronously from the CPU bus, enabling concurrent data movement and CPU execution. The M66591GP#RB1S uses DREQ/DACK handshake for DMA flow control.
What clock frequencies are supported by the M66591GP#RB1S, and how is PLL configured?
The M66591GP#RB1S accepts 12 MHz, 24 MHz, or 48 MHz crystal or external clock input via XIN/XOUT. The Xtal[1:0] bits (USB Transceiver Control Register 0) select the input frequency; PLLC and SCKE bits enable PLL operation and internal clock distribution. The PLL locks to generate precise Hi-Speed timing - configuration sequence requires stable oscillation before enabling PLL and USB clock (SCKE), as defined in Section 3.1 of the datasheet. The M66591GP#RB1S does not support 6 MHz or other frequencies.
M66591GP#RB1S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- -
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- -
- Core Size:
- -
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- -
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- -
- Oscillator Type:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
M66591GP#RB1S FAQ
1.How can I place an order for M66591GP#RB1S through Aetrix?
Please submit a Request for Quotation (RFQ) for M66591GP#RB1S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M66591GP#RB1S reliable?
The price and inventory of M66591GP#RB1S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M66591GP#RB1S is usually 5 days.
3.What payment methods are accepted for M66591GP#RB1S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M66591GP#RB1S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M66591GP#RB1S?
M66591GP#RB1S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M66591GP#RB1S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M66591GP#RB1S?
For technical support, including M66591GP#RB1S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M66591GP#RB1S requirements.
6.How does Aetrix verify that M66591GP#RB1S is sourced from the original manufacturer or authorized distributors?
All M66591GP#RB1S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M66591GP#RB1S meets industry standards.
7.What is the process for return or replacement of M66591GP#RB1S?
All M66591GP#RB1S units undergo pre-shipment inspection (PSI). If there is an issue with M66591GP#RB1S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M66591GP#RB1S part is unused and in its original packaging.
Return procedure for M66591GP#RB1S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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