STMicroelectronics M74HC112B1R
- Part No.:
- M74HC112B1R
- Manufacturer:
- STMicroelectronics
- Category:
- Flip Flops
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
M74HC112B1R.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,994
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Product details
Overview
M74HC112B1R from STMicroelectronics is a high-speed CMOS dual J-K flip-flop with independent preset and clear inputs per stage, edge-triggered on the falling clock edge, operating from 2V to 6V supply, delivering 79MHz max clock frequency (typ.) at 6V, 4mA output drive, and 2µA quiescent current - used in synchronous logic control, state machines, and clock-domain synchronization in industrial PLC modules.
For engineers reviewing the M74HC112B1R datasheet, M74HC112B1R pinout, M74HC112B1R application, or M74HC112B1R equivalent, key selection criteria include negative-edge triggering behavior, asynchronous set/clear timing margins, propagation delay symmetry (tPLH ≅ tPHL), and DIP-16 package compatibility with legacy 74-series board layouts.
Technical Context
The M74HC112 implements two independent, negative-edge-triggered J-K bistables with fully asynchronous active-low preset (PR) and clear (CLR) inputs. Each flip-flop accepts J/K data during high clock phase and latches on clock fall, supporting toggle, set, reset, and hold functions per truth table.
It uses silicon gate C2MOS technology for low power and high noise immunity (VNIH/VNIL = 28% VCC min), features symmetrical output drive (|IOH| = IOL = 4mA min), and operates across –55°C to +125°C with balanced propagation delays and wide voltage margin (2–6V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (74HC), pin- and function-compatible with 74LS112 |
| Max Clock Frequency | 79 MHz (typ.) at VCC = 6V - enables high-speed state sequencing in real-time controllers |
| Supply Voltage Range | 2V to 6V - supports mixed-voltage system interfacing (e.g., 3.3V logic with 5V peripherals) |
| Quiescent Current | 2 µA (max) at TA = 25°C - critical for battery-backed or ultra-low-power retention modes |
| Output Drive | ±4 mA (min) - sufficient to directly drive multiple 74HC inputs without buffering |
| Propagation Delay | tPLH/tPHL = 14 ns (typ.) at VCC = 6V - ensures tight timing budgets in synchronous pipelines |
| Input Noise Immunity | VNIH/VNIL = 28% VCC (min) - rejects EMI in noisy industrial environments |
Pinout & Package
Package: 16-pin plastic DIP (Dual In-line Package), 0.3-inch body width, through-hole mount, JEDEC MS-001 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | 1CK, 2CK | Falling-edge clock inputs - trigger state change on clock transition from HIGH to LOW |
| 2, 12 | 1K, 2K | Active-HIGH J-K data inputs - define next-state logic per flip-flop (K = 1 enables reset on clock) |
| 3, 11 | 1J, 2J | Active-HIGH J-K data inputs - define next-state logic (J = 1 enables set on clock) |
| 4, 10 | 1PR, 2PR | Asynchronous active-LOW preset - forces Q = HIGH independent of clock |
| 5, 9 | 1Q, 2Q | True outputs - provide registered logic state for downstream combinational logic |
| 6, 7 | 1Q̅, 2Q̅ | Complement outputs - enable direct implementation of toggle or differential signaling |
| 14, 15 | 1CLR, 2CLR | Asynchronous active-LOW clear - forces Q = LOW independent of clock |
| 8 | GND | Ground reference (0 V) - return path for all internal currents and I/O |
| 16 | VCC | Positive supply (2–6 V) - powers internal logic and defines logic threshold levels |
Key Features
| Feature | Design Value |
|---|---|
| Negative-edge clock triggering | Enables precise synchronization with inverted clock domains and avoids metastability in cascaded stages |
| Independent asynchronous preset/clear | Allows per-stage initialization or fault recovery without halting global clock distribution |
| Symmetrical output impedance | Ensures matched rise/fall times and minimizes skew between Q and Q̅ outputs |
| Wide temperature range | –55°C to +125°C operation supports deployment in automotive engine control and industrial motor drives |
| ESD-protected inputs | Withstands ±20 mA input diode current - reduces need for external transient protection in ruggedized designs |
Applications
| Industrial PLC Sequencers | Digital Test Equipment Counters |
|---|---|
Use Scenario: Implementing multi-step machine cycle timers with manual override and emergency stop logic. IC Role / Device Role / Timing Role: Dual J-K flip-flop provides two independent state registers synchronized to a common clock, with asynchronous clear enabling immediate halt. Use Value: Negative-edge triggering prevents race conditions during step transitions; preset/clear pins allow deterministic startup and fault recovery without software intervention. |
Use Scenario: Building 4-bit binary counters using cascaded J-K stages in automated test fixture pattern generators. IC Role / Device Role / Timing Role: Each M74HC112 supplies two toggle-capable bits; Q̅ output feeds next stage's clock to achieve divide-by-2 functionality. Use Value: 79 MHz max clock rate supports >30 MHz test pattern generation; symmetrical delays ensure clean carry propagation across bit boundaries. |
| Legacy System Upgrades | Motor Control State Machines |
Use Scenario: Replacing obsolete 74LS112 in aging instrumentation hardware while retaining PCB layout and firmware. IC Role / Device Role / Timing Role: Pin- and function-compatible drop-in replacement with identical truth table and DIP-16 footprint. Use Value: 2V–6V supply range allows direct substitution without level-shifting; 2µA ICC enables lower standby power than TTL equivalents. |
Use Scenario: Managing commutation sequence states in 3-phase BLDC motor drivers with Hall sensor feedback. IC Role / Device Role / Timing Role: Stores rotor position state and generates gated PWM enable signals via Q/Q̅ outputs driving gate drivers. Use Value: –55°C to +125°C rating ensures reliability under motor heat soak; high noise immunity prevents false triggering near power switches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC112N | Same logic function and pinout; TI version specifies fMAX = 60 MHz (typ.) at 6V, higher ICC = 4 µA (max) | Valid for same PCB footprints but may limit max system clock in high-frequency sequencers | Select when TI supply chain preference applies and 60 MHz suffices |
| CD74HC112E | TI variant with identical AC specs; wider VCC range (2–6V), but only rated for –40°C to +85°C operation | Not suitable for extended temperature deployments (e.g., under-hood automotive) | Prefer for commercial-grade cost-sensitive designs where temp range is not critical |
Compared with SN74HC112N and CD74HC112E, M74HC112B1R delivers superior high-speed performance (79 MHz vs. 60 MHz) and extended temperature support (–55°C to +125°C), making it optimal for industrial and automotive timing-critical state machines where reliability under thermal stress is mandatory.
Availability
M74HC112B1R is available at Aetrix Electronics and suitable for industrial PLC sequencers, digital test equipment counters, legacy system upgrades, and motor control state machines requiring stable component supply and long-term obsolescence mitigation.
Supply support for M74HC112B1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with vertical manufacturing and broad analog/mixed-signal portfolio.
M74HC112 belongs to ST's legacy HC logic family, designed for robust, low-power, pin-compatible replacements of bipolar 74-series devices in industrial control, instrumentation, and infrastructure systems.
FAQ
Is M74HC112B1R compatible with 5V TTL logic interfaces?
Yes - its input thresholds (VIH = 3.15V min, VIL = 1.35V max at VCC = 4.5V) and output voltages (VOH = 4.4V min, VOL = 0.26V max at 4mA load) meet TTL interface requirements. It can directly drive 74LS inputs and accept 74LS outputs without level shifters when powered at 5V.
What is the minimum pulse width required on CLR/PR inputs?
The minimum active pulse width for CLR and PR is 4 ns (typ.) at VCC = 6V, and 19 ns (max) over full temperature range (–55°C to +125°C). This ensures reliable asynchronous reset/set even in fast-clocked systems with short glitch windows.
Does M74HC112B1R support hot insertion or live circuit swapping?
No - it lacks Ioff protection or power-up 3-state. Applying VCC before GND or inserting while powered risks latch-up due to internal parasitic SCR structures. Power sequencing must follow GND-first, VCC-second, and signal-last order per STMicroelectronics application guidelines.
Can both flip-flops share the same clock while maintaining independent J/K control?
Yes - pins 1 and 13 are separate clock inputs, but they may be tied together externally. Each stage retains independent J, K, PR, and CLR inputs, allowing synchronized updates with distinct next-state definitions - essential for dual-channel counter or register applications.
M74HC112B1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74HC
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 79 MHz
- Max Propagation Delay @ V, Max CL:
- 21ns @ 6V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 2 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
M74HC112B1R FAQ
1.How can I place an order for M74HC112B1R through Aetrix?
Please submit a Request for Quotation (RFQ) for M74HC112B1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M74HC112B1R reliable?
The price and inventory of M74HC112B1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M74HC112B1R is usually 5 days.
3.What payment methods are accepted for M74HC112B1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M74HC112B1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M74HC112B1R?
M74HC112B1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M74HC112B1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M74HC112B1R?
For technical support, including M74HC112B1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M74HC112B1R requirements.
6.How does Aetrix verify that M74HC112B1R is sourced from the original manufacturer or authorized distributors?
All M74HC112B1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M74HC112B1R meets industry standards.
7.What is the process for return or replacement of M74HC112B1R?
All M74HC112B1R units undergo pre-shipment inspection (PSI). If there is an issue with M74HC112B1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M74HC112B1R part is unused and in its original packaging.
Return procedure for M74HC112B1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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