STMicroelectronics M74HC367RM13TR
- Part No.:
- M74HC367RM13TR
- Manufacturer:
- STMicroelectronics
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M74HC367RM13TR.pdf
- Description:
- IC BUFFER NON-INVERT 6V 16SO
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M74HC367RM13TR from STMicroelectronics is a high-speed CMOS hex bus buffer with non-inverting 3-state outputs, designed for bidirectional data bus interfacing in digital systems. It features six independent buffers-four controlled by G1 and two by G2-with symmetrical output drive (|IOH| = IOL ≥ 6 mA), propagation delay of 9 ns (typ. at VCC = 6 V), and operation across 2 V to 6 V supply. Used in microcontroller address/data bus isolation and memory interface control.
For engineers reviewing the M74HC367RM13TR datasheet, M74HC367RM13TR pinout, M74HC367RM13TR application, or M74HC367RM13TR equivalent, key selection criteria include 3-state enable timing (tPZL/tPLZ ≤ 23 ns at 6 V), wide VCC range (2–6 V), high noise immunity (VNIH/VNIL ≥ 28% VCC), and TSSOP-16 package compatibility with space-constrained PCB layouts.
Technical Context
The M74HC367RM13TR implements dual-group 3-state control logic: G1 enables pins 1Y–4Y when low; G2 enables 5Y–6Y when low. All inputs include ESD protection diodes and transient voltage clamping, supporting robust operation in noisy industrial environments.
Its C2MOS silicon gate process delivers balanced tPLH ≅ tPHL propagation delays and symmetrical output impedance, enabling clean signal integrity in both rising and falling edges under capacitive loads up to 150 pF. Input rise/fall time limits are specified per VCC (e.g., ≤400 ns at 6 V), ensuring reliable timing margin in mixed-voltage systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2 V to 6 V - supports direct interface with 3.3 V and 5 V logic families without level shifters |
| tPD (Typ.) | 9 ns at VCC = 6 V - enables high-speed bus buffering in systems with >50 MHz clock domains |
| IOL / IOH | ≥6 mA - drives standard TTL loads and multiple CMOS inputs without fanout limitation |
| VNIH / VNIL | ≥28% VCC - rejects common-mode noise on shared bus lines in electrically noisy enclosures |
| ICC (Max) | 4 µA at TA = 25°C - enables ultra-low static power in battery-backed or always-on subsystems |
| Operating Temp | −55°C to +125°C - qualified for extended industrial and automotive under-hood applications |
| Output Leakage | ±10 µA max at −55°C to +125°C - ensures stable high-impedance state during sleep or hot-swap events |
Pinout & Package
TSSOP-16 (Thin Shrink Small Outline Package) with 0.65 mm pitch, 5.0 × 4.4 mm body, and exposed pad not present. RoHS-compliant, moisture sensitivity level MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | G1, G2 | Active-low 3-state enable inputs - separate control for two buffer groups improves bus arbitration flexibility |
| 2, 4, 6, 10, 12, 14 | 1A–6A | Non-inverting data inputs - direct connection to MCU port pins or memory address lines |
| 3, 5, 7, 9, 11, 13 | 1Y–6Y | Buffered non-inverting outputs - drive downstream logic while isolating source from bus loading |
| 8 | GND | Digital ground reference - must be low-inductance connection to minimize switching noise coupling |
| 16 | VCC | Positive supply - decoupling capacitor (100 nF ceramic) required within 5 mm of pin for AC stability |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 3-state control | G1/G2 separation allows selective activation of four vs. two outputs - reduces contention in multi-master bus arbitration |
| High noise immunity | VNIH/VNIL ≥ 28% VCC ensures reliable logic recognition even with ±300 mV ground bounce |
| Balanced propagation delay | tPLH ≅ tPHL minimizes duty cycle distortion in clock-forwarding or strobe distribution paths |
| Wide temperature range | −55°C to +125°C operation validated per AEC-Q100 stress test conditions for automotive ECUs |
| ESD-protected inputs | Integrated diode clamps withstand ≥2 kV HBM - eliminates need for external TVS on board-level I/O traces |
Applications
| Microcontroller Bus Isolation | Memory Address Latching |
|---|---|
Use Scenario: Isolating an ARM Cortex-M4 GPIO port from a shared 16-bit parallel bus connected to multiple peripherals. IC Role / Device Role / Timing Role: Non-inverting 3-state buffer providing direction-controlled data path isolation with <23 ns enable/disable latency. Use Value: Prevents bus contention during simultaneous peripheral access; enables deterministic timing for DMA transfers. | Use Scenario: Driving SRAM address lines from a multiplexed CPU address/data bus using external latch control. IC Role / Device Role / Timing Role: Hex buffer latches and stabilizes address bits during AD bus demultiplexing phase. Use Value: Eliminates address skew between bits; maintains setup/hold margins for 10 ns SRAM access cycles. |
| Industrial PLC I/O Expansion | Automotive Body Control Module |
Use Scenario: Expanding digital input capability in a DIN-rail mounted PLC by buffering isolated optocoupler outputs to the main controller. IC Role / Device Role / Timing Role: Signal conditioning buffer translating 24 V opto signals (via level shifter) into clean 3.3 V logic levels. Use Value: Rejects 2 kV surge-induced transients on field wiring; sustains operation at 85°C ambient. | Use Scenario: Interfacing LIN transceiver status flags and sensor diagnostics to a central BCM microcontroller over a shared diagnostic bus. IC Role / Device Role / Timing Role: Bidirectional bus buffer enabling readback of transceiver registers without interrupting active LIN communication. Use Value: Enables concurrent diagnostics and real-time bus operation; meets ISO 11898-3 EMC immunity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC367N | DIP-16 package; higher ICC (80 µA max); tPD = 14 ns (typ. at 6 V) | Lacks TSSOP thermal performance; unsuitable for high-density or thermally constrained layouts | Select for through-hole prototyping or legacy DIP-based industrial controllers |
| 74LVC367PW | Lower VCC range (1.65–3.6 V); higher drive (24 mA); faster tPD (3.2 ns typ. at 3.3 V) | Not compatible with 5 V systems; requires level translation when interfacing with legacy 5 V peripherals | Select for modern 3.3 V-only designs prioritizing speed and low-voltage operation |
Compared with SN74HC367N and 74LVC367PW, the M74HC367RM13TR uniquely balances 2–6 V interoperability, TSSOP thermal efficiency, and industrial-grade temperature range - making it optimal for mixed-voltage embedded systems requiring long-term supply stability.
Availability
M74HC367RM13TR is available at Aetrix Electronics and suitable for microcontroller bus isolation, memory address latching, industrial PLC I/O expansion, and automotive body control modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for M74HC367RM13TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with vertical manufacturing capabilities and AEC-Q100-qualified product lines.
The M74HC367 belongs to ST's high-reliability HC logic family, engineered for robust operation in harsh environments including factory automation, transportation infrastructure, and under-hood automotive electronics.
FAQ
What is the maximum capacitive load the M74HC367RM13TR can drive while maintaining specified tPLH/tPHL?
The device is characterized for CL = 50 pF and CL = 150 pF loads in AC specifications. At CL = 150 pF and VCC = 6 V, tPLH/tPHL remains ≤160 ns (max), confirming stable operation into heavy bus capacitance typical of backplane or multi-drop configurations. Derating is not required up to this value.
Can G1 and G2 be tied together for single-enable operation?
Yes - G1 and G2 may be connected to a common control signal. This configures all six buffers as a unified group, simplifying logic design where full-bus enable is sufficient. No additional components or timing penalties are introduced, as both inputs share identical electrical thresholds and propagation characteristics.
Does the M74HC367RM13TR support hot insertion or live bus swapping?
No - the device lacks powered-off protection (Ioff) or bus-hold circuitry. Applying input signals while VCC = 0 V may forward-bias internal protection diodes, risking latch-up or excessive current. Power sequencing must ensure VCC is stable before asserting any inputs or enables.
How does the 4 µA max ICC at 25°C translate to system-level power budgeting?
At 6 V and 25°C, quiescent current is ≤4 µA - contributing just 24 µW to total system power. Even across six channels, static consumption remains below 0.15 mW, making it viable for always-on monitoring circuits in energy-harvesting or battery-operated edge nodes with multi-year runtime targets.
M74HC367RM13TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 7.8mA, 7.8mA
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
M74HC367RM13TR FAQ
1.How can I place an order for M74HC367RM13TR through Aetrix?
Please submit a Request for Quotation (RFQ) for M74HC367RM13TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of M74HC367RM13TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M74HC367RM13TR is usually 5 days.
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5.How can I obtain technical support or documentation for M74HC367RM13TR?
For technical support, including M74HC367RM13TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M74HC367RM13TR requirements.
6.How does Aetrix verify that M74HC367RM13TR is sourced from the original manufacturer or authorized distributors?
All M74HC367RM13TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M74HC367RM13TR meets industry standards.
7.What is the process for return or replacement of M74HC367RM13TR?
All M74HC367RM13TR units undergo pre-shipment inspection (PSI). If there is an issue with M74HC367RM13TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M74HC367RM13TR part is unused and in its original packaging.
Return procedure for M74HC367RM13TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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