STMicroelectronics M74HC390B1R

Overview

M74HC390B1R from STMicroelectronics is a high-speed CMOS dual decade counter with two independent ripple-carry counters, each comprising a divide-by-2 and divide-by-5 stage, operating across 2V–6V supply, delivering 79MHz max clock frequency at 6V, and featuring asynchronous active-low clear inputs for count truncation in timing and frequency-division circuits.

For engineers reviewing the M74HC390B1R datasheet, M74HC390B1R pinout, M74HC390B1R application, or M74HC390B1R equivalent, this device supports BCD and bi-quinary counting modes, edge-triggered negative-clock operation, low-power static current (≤4µA), and robust noise immunity (≥28% VCC) - critical for industrial control logic, instrumentation timing, and legacy TTL-compatible digital systems.

Technical Context

The M74HC390B1R implements two cascaded 4-bit synchronous counters per section: one triggered by CLOCK A (divide-by-2 output) and the other by CLOCK B (divide-by-5 output), enabling configurable division ratios up to ÷100. Each counter advances on the high-to-low transition of its respective clock input.

It features fully independent clear inputs per counter (pins 1 & 15 for Counter 1, pins 2 & 14 for Counter 2), allowing selective reset without affecting the other counter. All inputs include ESD protection diodes, and outputs drive ±5.2mA at 6V with guaranteed VOL ≤0.40V and VOH ≥5.60V.

Key Specifications

Pinout & Package

DIP-16 plastic dual in-line package with 2.54 mm lead pitch, 20.0 mm body width, and through-hole mounting compatibility.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual decade counter applications.

Compared with SN74HC390N and CD74HC390E, the M74HC390B1R offers the widest operating temperature range (−55°C to +125°C), making it uniquely suited for under-hood automotive modules, downhole oilfield sensors, and high-reliability industrial controllers where thermal stability is non-negotiable.

Availability

M74HC390B1R is available at Aetrix Electronics and suitable for industrial timer modules, digital panel meters, legacy system upgrades, and frequency division circuits requiring stable component supply, long-term lifecycle support, and guaranteed DIP-16 through-hole availability.

Supply support for M74HC390B1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and logic devices for industrial, automotive, and consumer markets.

The M74HC390B1R belongs to ST's legacy HC logic family, engineered for pin-compatible upgrades of 74-series TTL counters with enhanced speed, noise immunity, and power efficiency in fixed-function digital timing applications.

FAQ

What is the maximum clock frequency supported by M74HC390B1R at 5V supply?

At VCC = 4.5V, the M74HC390B1R supports a maximum clock frequency of 65 MHz (typ.) for CLOCK A → QA propagation, and 67 MHz (typ.) for CLOCK B → QB. These values are measured under CL = 50 pF load and input rise/fall times ≤500 ns, per ST's July 2006 Rev 2 datasheet Table 7.

Can M74HC390B1R operate in bi-quinary mode without external components?

Yes - bi-quinary mode is enabled by connecting Counter 1's QD output to Counter 2's CLOCK A input, and Counter 2's QD output to Counter 1's CLOCK A input, as shown in Figure 3 of the datasheet. No additional logic gates or resistors are required for this configuration.

Is M74HC390B1R RoHS-compliant and lead-free?

Yes - the M74HC390B1R uses ST's ECOPACK® packaging with lead-free second-level interconnects, compliant with JEDEC JESD97 and EU RoHS Directive 2011/65/EU. The inner box label and package marking indicate "ECOPACK" and lead-free status.

How does the clear function behave during clock transitions?

The clear inputs (pins 1, 2, 14, 15) are asynchronous and active-low: asserting CLEAR immediately forces all Q outputs low within tPHL(CLEAR→Qn) ≤32 ns (max at VCC = 6V), regardless of clock phase or state - ensuring deterministic reset even mid-count cycle.