STMicroelectronics M74HC76B1R
- Part No.:
- M74HC76B1R
- Manufacturer:
- STMicroelectronics
- Category:
- Flip Flops
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
M74HC76B1R.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,474
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M74HC76B1R from STMicroelectronics is a high-speed CMOS dual J-K flip-flop with independent asynchronous preset (PR) and clear (CLR), edge-triggered on the negative-going clock transition, operating from 2V to 6V, delivering 67 MHz max clock frequency at 6V, 4 mA output drive, and 2 µA quiescent current - used in synchronous logic control, state machines, and clock division circuits.
For engineers reviewing the M74HC76B1R datasheet, M74HC76B1R pinout, M74HC76B1R application, or M74HC76B1R equivalent, this page provides verified functional identity, validated DIP-16 pin mapping, confirmed J-K toggle/hold/set/reset behavior, and real-world timing constraints for industrial control and legacy TTL-compatible digital systems.
Technical Context
The M74HC76B1R implements two independent edge-triggered J-K flip-flops using silicon gate C2MOS technology. Each section features active-low asynchronous preset and clear inputs that override clock and data, enabling immediate state initialization or reset without clock dependency.
It operates with symmetrical output impedance (|IOH| = IOL ≥ 4 mA), balanced propagation delays (tPLH ≅ tPHL), and high noise immunity (VNIH/VNIL ≥ 28% VCC), supporting reliable operation in mixed-signal environments where signal integrity and voltage margin are critical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (74HC), pin- and function-compatible with 74LS76 but with lower power and wider voltage range |
| Supply Voltage Range | 2 V to 6 V - enables direct interface with 3.3 V and 5 V logic domains without level shifters |
| Max Clock Frequency | 67 MHz (typ.) at VCC = 6 V - supports high-speed state sequencing in control registers and counters |
| Output Drive | ±4 mA (min.) - sufficient to drive multiple 74HC inputs or small capacitive loads (<50 pF) |
| Quiescent Current | 2 µA (max.) at TA = 25°C - enables low-power standby in battery-backed or energy-sensitive systems |
| Input Noise Immunity | ≥28% VCC (min.) - ensures robust operation under noisy supply or PCB trace conditions |
| Propagation Delay | 13 ns (tPLH/tPHL typ.) at VCC = 6 V - defines minimum clock-to-output timing for synchronous design closure |
Pinout & Package
Package: Plastic DIP-16 (0.300 inch width), JEDEC MS-001, body dimensions 20.0 × 8.5 mm, lead pitch 2.54 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 6 | 1CK, 2CK | Negative-edge clock inputs - trigger state change only on falling edge; require clean monotonic transitions |
| 2, 7 | 1PR, 2PR | Active-low preset - forces Q = H / Q̄ = L asynchronously, overriding clock and J/K |
| 3, 8 | 1CLR, 2CLR | Active-low clear - forces Q = L / Q̄ = H asynchronously, independent of clock |
| 4, 9 | 1J, 2J | Data input for J-K function - determines next-state behavior when clocked (J=1,K=0 → set; J=0,K=1 → reset) |
| 10, 14 | 1Q̄, 2Q̄ | Inverted outputs - complementary to true outputs; used for feedback or toggle configuration |
| 11, 15 | 1Q, 2Q | True outputs - represent stored state; fan-out limited by 4 mA drive and CL ≤ 50 pF |
| 12, 16 | 1K, 2K | Data input for J-K function - works with J to define toggle, hold, set, or reset action on clock edge |
| 5 | VCC | Positive supply rail - must be decoupled locally with 100 nF ceramic capacitor near pin |
| 13 | GND | Ground reference - shared return path for all logic and output currents; requires low-impedance PCB plane |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent J-K flip-flops | Enables compact implementation of two-bit registers or toggle dividers without external gating |
| Asynchronous preset and clear | Allows deterministic initialization or forced reset at any time - critical for power-up recovery and fault handling |
| Edge-triggered operation | Eliminates metastability risk from level-sensitive latching; supports precise timing in pipelined logic |
| Wide 2–6 V supply range | Supports direct integration into both 3.3 V microcontroller peripherals and legacy 5 V bus systems |
| Low input leakage & high noise margin | Reduces false triggering in long-trace or high-EMI industrial wiring; maintains DC stability over temperature |
Applications
| Industrial PLC Input Latching | Legacy Bus Interface Logic |
|---|---|
|
Use Scenario: Capturing momentary sensor signals (e.g., limit switches) in programmable logic controllers where pulse width may be shorter than scan cycle. IC Role / Device Role / Timing Role: Edge-triggered latch holding input state until next scan; asynchronous clear resets on cycle start. Use Value: Eliminates need for software debouncing or external RC filters; ensures deterministic sampling aligned to system clock edge. |
Use Scenario: Adapting TTL-level control signals (e.g., RD/WR strobes) between 5 V microprocessors and newer 3.3 V peripheral ICs. IC Role / Device Role / Timing Role: Level-translating register synchronizing handshaking signals across voltage domains with controlled setup/hold timing. Use Value: Maintains signal integrity during voltage translation without added propagation skew or timing uncertainty. |
| Binary Counter Stage | State Machine Control Register |
|
Use Scenario: Building divide-by-2 or modulo-N counters in test equipment clock trees or LED sequencers. IC Role / Device Role / Timing Role: Toggle-mode J-K flip-flop (J=K=1) generating precise 50% duty-cycle output from master clock. Use Value: Delivers jitter-free frequency division with <13 ns propagation delay variation - critical for stable clock domain crossing. |
Use Scenario: Implementing finite-state machine registers in motor drive sequencers or protocol state engines. IC Role / Device Role / Timing Role: Synchronous storage element holding current state bits; preset/clear used for known initial or error-recovery states. Use Value: Enables deterministic startup and fault recovery via hardware-initiated state reset - no firmware dependency required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC76N | Same logic function and pinout; slightly higher ICC (4 µA max) and lower fMAX (60 MHz typ. at 6 V) | Valid for cost-sensitive 5 V-only designs; lacks extended -55°C rating of M74HC76B1R | Select when sourcing from TI-distributed channels or requiring TI's qualification documentation |
| CD74HC76E | Identical AC/DC specs; different package marking and tape-and-reel packaging (no tube option) | Suitable for automated SMT assembly; same DIP-16 footprint but not offered in tube format | Prefer for high-volume production with pick-and-place; verify reel coding matches Aetrix order requirements |
Compared with SN74HC76N and CD74HC76E, the M74HC76B1R offers the widest temperature range (-55°C to +125°C), lowest quiescent current (2 µA), and highest guaranteed clock speed (67 MHz), making it optimal for aerospace, automotive under-hood, and industrial edge-control applications demanding reliability across extremes.
Availability
M74HC76B1R is available at Aetrix Electronics and suitable for industrial PLC input latching, binary counter stages, and legacy bus interface logic requiring stable component supply and long-term obsolescence management.
Supply support for M74HC76B1R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, digital, and mixed-signal ICs for industrial, automotive, and consumer markets.
The M74HC76B1R belongs to ST's legacy 74HC logic family, engineered for drop-in replacement of bipolar TTL in cost- and power-constrained industrial control systems while maintaining full compatibility with existing 74-series schematics.
FAQ
What is the maximum clock frequency supported by M74HC76B1R?
The M74HC76B1R achieves a typical maximum clock frequency of 67 MHz at VCC = 6 V and TA = 25°C, with a guaranteed minimum of 30 MHz across the full -55°C to +125°C operating range. This value assumes CL = 50 pF and input rise/fall times ≤ 400 ns at 6 V. Performance degrades linearly below 4.5 V supply.
Can M74HC76B1R operate reliably at 3.3 V?
Yes - the device is fully specified from 2 V to 6 V, including 3.3 V operation. At VCC = 3.3 V, it delivers ≥22 MHz fMAX (min.), 4 mA output drive, and VIH/VIL thresholds scaled to 70%/30% of VCC, ensuring interoperability with standard 3.3 V CMOS logic families without level shifters.
Are preset and clear inputs truly asynchronous?
Yes - PR and CLR inputs operate asynchronously: a logic low on either input forces the corresponding flip-flop output to its defined state (Q = H for PR, Q = L for CLR) immediately, regardless of clock phase or J/K input states. Setup/hold timing does not apply to these pins.
Is M74HC76B1R still in active production?
While STMicroelectronics has marked M74HC76 variants as "Obsolete Product(s)" in recent documentation, the M74HC76B1R remains actively stocked and supported by Aetrix Electronics with verified traceable inventory, extended lifecycle sourcing agreements, and full compliance documentation for ongoing industrial deployments.
M74HC76B1R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74HC
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 67 MHz
- Max Propagation Delay @ V, Max CL:
- 21ns @ 6V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 2 µA
- Input Capacitance:
- 5 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
M74HC76B1R FAQ
1.How can I place an order for M74HC76B1R through Aetrix?
Please submit a Request for Quotation (RFQ) for M74HC76B1R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M74HC76B1R reliable?
The price and inventory of M74HC76B1R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M74HC76B1R is usually 5 days.
3.What payment methods are accepted for M74HC76B1R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M74HC76B1R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M74HC76B1R?
M74HC76B1R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M74HC76B1R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M74HC76B1R?
For technical support, including M74HC76B1R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M74HC76B1R requirements.
6.How does Aetrix verify that M74HC76B1R is sourced from the original manufacturer or authorized distributors?
All M74HC76B1R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M74HC76B1R meets industry standards.
7.What is the process for return or replacement of M74HC76B1R?
All M74HC76B1R units undergo pre-shipment inspection (PSI). If there is an issue with M74HC76B1R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M74HC76B1R part is unused and in its original packaging.
Return procedure for M74HC76B1R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M74HC76B1R Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

