STMicroelectronics M93C46-WMN6TP
- Part No.:
- M93C46-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M93C46-WMN6TP.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:35,419
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Product details
Overview
M93C46-WMN6TP from STMicroelectronics is a 1-Kbit MICROWIRE™-interface serial EEPROM with dual x8/x16 organization, operating from 2.5 V to 5.5 V supply and supporting up to 2 MHz clock frequency. It delivers byte/word/page write within 5 ms, features READY/BUSY signaling, and is rated for -40 °C to +85 °C operation in SO8N (150 mil) package - used for configuration storage in industrial controllers and embedded boot loaders.
For engineers reviewing the M93C46-WMN6TP datasheet, M93C46-WMN6TP pinout, M93C46-WMN6TP application, or M93C46-WMN6TP equivalent, key selection criteria include MICROWIRE™ bus compatibility, 128-byte / 64-word memory mapping, ORG-selectable organization, fast 5 ms write cycle, and 4 million write endurance at 25°C.
Technical Context
The M93C46-WMN6TP implements a static CMOS-based MICROWIRE™ protocol interface with start-bit–driven instruction framing, supporting READ, WRITE, ERASE, WEN/WDS, ERAL, and WRAL commands. Its dual-memory organization is selected via the ORG pin: tied to VSS for x8 (128 bytes), unconnected or tied to VCC for x16 (64 words).
Internal self-timed programming cycles are triggered by falling edge of Chip Select (S) after full instruction reception; completion is signaled via Q pin (READY=high, BUSY=low). An on-chip clock pulse counter validates instruction length to prevent corruption from noise-induced bit shifts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1024 bits (128 bytes or 64 words) |
| Interface | MICROWIRE™ serial bus (3-wire: S, C, D/Q) |
| Supply voltage | 2.5 V to 5.5 V - supports legacy 3.3 V and 5 V systems without level shifters |
| Max clock frequency | 2 MHz - enables high-speed configuration reads during boot |
| Write cycle time | ≤5 ms - allows rapid parameter updates in real-time control loops |
| Data retention | 200 years at 55 °C - ensures long-term reliability in sealed industrial enclosures |
| Endurance | 4 million write cycles at 25 °C - suitable for frequent calibration or logging use cases |
Pinout & Package
Package: SO8N (150 mil width), 8-pin plastic small outline, ECOPACK2-compliant, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (S) | Chip Select | Active-low enable; must be held low between instructions to avoid spurious writes |
| 2 (C) | Serial Clock | Input; rising edge samples D and clocks Q; requires external pull-down if MCU enters Hi-Z state |
| 3 (D) | Serial Data Input | Input; carries start bit, op-code, address, and data; sampled on C rising edge |
| 4 (ORG) | Organization Select | Input; VSS = x8 mode (128 bytes), open/VCC = x16 mode (64 words); affects address width and instruction timing |
| 5 (Q) | Serial Data Output / READY-BUSY | Output; returns data during READ, signals BUSY (low) or READY (high) during programming |
| 6 (VSS) | Ground | Reference return path; decoupling capacitor (10–100 nF) required near pin |
| 7 (VCC) | Supply Voltage | 2.5–5.5 V DC; POR circuit prevents writes during power ramp-up |
| 8 (DU) | Do Not Use | No internal connection; may be left floating, tied to VCC, or tied to VSS per layout convenience |
Key Features
| Feature | Design Value |
|---|---|
| Dual memory organization | Hardware-selectable x8 (128-byte) or x16 (64-word) addressing via ORG pin - eliminates software remapping overhead |
| READY/BUSY status on Q pin | Real-time hardware feedback replaces polling delays - reduces firmware latency in time-critical writes |
| On-chip clock pulse counter | Validates exact instruction bit count (e.g., 25 cycles for x16 WRITE) - prevents glitch-induced memory corruption |
| Enhanced ESD protection | 4000 V HBM - meets industrial I/O robustness requirements without external TVS diodes |
| Power-on reset (POR) | Automatic WEN disable until VCC crosses threshold - eliminates need for external reset sequencing |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) Trim Settings |
|---|---|
Use Scenario: Storing calibrated sensor offsets, I/O mapping, and user-defined logic states in programmable logic controllers. IC Role / Device Role / Timing Role: Non-volatile configuration register accessed during cold boot and runtime reconfiguration. Use Value: 4 million write cycles support field recalibration every 8 hours for >10 years; 200-year data retention avoids replacement in sealed cabinets. | Use Scenario: Retaining seat/mirror position, lighting profiles, and door lock preferences across vehicle ignition cycles. IC Role / Device Role / Timing Role: MICROWIRE™-connected parameter store interfaced directly to 8-bit microcontroller with no glue logic. Use Value: 5 ms page write enables saving all 128 bytes in one burst during ignition-off sequence; -40 °C to +85 °C rating matches under-hood BCM thermal envelope. |
| Medical Infusion Pump Calibration Data | Smart Energy Meter Firmware Patch Storage |
Use Scenario: Holding factory-calibrated flow rate coefficients and safety thresholds updated only during service intervals. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage isolated from main MCU flash; accessed via dedicated SPI-like MICROWIRE™ bus. Use Value: WEN/WDS instruction locking prevents accidental overwrites during firmware updates; 4000 V HBM withstands ESD events in clinical environments. | Use Scenario: Storing encrypted firmware patches downloaded over PLC or RF link, applied before next meter reboot. IC Role / Device Role / Timing Role: Standalone patch buffer enabling atomic update rollback - erased only after successful verification. Use Value: ERAL and WRAL instructions allow full-memory erase/write in single command (14 cycles); 2.5 V min supply ensures operation during brown-out conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT93C46DN-SH-T | Same 1-Kbit MICROWIRE™ interface, but 1.8–5.5 V supply range (R-version); no DU pin; TSSOP8 only | Preferred where ultra-low-voltage operation (<2.5 V) or smaller footprint is required | Select when system operates down to 1.8 V or board space constraints favor TSSOP8 over SO8N |
| M93C46-RMN6TP | Identical pinout and functionality, but extended 1.8–5.5 V supply range; same SO8N package and timing | Drop-in replacement where wider VCC range is needed without changing layout | Choose for new designs targeting battery-powered or mixed-voltage systems; not recommended for legacy 5 V-only rails due to lower noise margin |
Compared with AT93C46DN-SH-T and M93C46-RMN6TP, the M93C46-WMN6TP offers optimal noise immunity and timing margin in fixed 3.3 V/5 V industrial systems, while its SO8N package provides proven manufacturability and thermal performance in high-reliability assemblies.
Availability
M93C46-WMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, automotive BCMs, medical infusion pumps, and smart energy meters requiring stable component supply, long-life data retention, and proven MICROWIRE™ interoperability.
Supply support for M93C46-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering silicon solutions for automotive, industrial, and embedded applications since 1987.
The M93Cxx series targets cost-sensitive, high-reliability serial configuration storage - designed specifically for MICROWIRE™-equipped microcontrollers in space-constrained, thermally demanding environments.
FAQ
What is the function of the ORG pin on M93C46-WMN6TP?
The ORG pin selects memory organization: grounded (VSS) configures the device as 128 bytes (x8), while left open or tied to VCC configures it as 64 words (x16). This changes address width (7-bit vs. 6-bit) and instruction timing - no software reconfiguration is needed once hardware-set.
How does the READY/BUSY signal operate on the Q pin?
During WRITE, ERASE, WRAL, or ERAL operations, the Q pin outputs LOW (BUSY) when Chip Select (S) is HIGH; it transitions to HIGH (READY) upon completion. This hardware flag eliminates polling delays and enables deterministic firmware timing - no external components are required.
Can M93C46-WMN6TP be used with standard SPI interfaces?
No - it uses the MICROWIRE™ protocol, which differs from SPI in clock polarity, phase, and instruction framing (start bit + op-code + address + data). Direct SPI connection will fail; a GPIO-bit-banged driver or MCU with configurable MICROWIRE™ peripheral is required.
Is the DU pin required to be connected?
No - the DU (Do Not Use) pin has no internal connection and serves only for STMicroelectronics test purposes. It may be left unconnected, tied to VCC, or tied to VSS based on PCB routing convenience; no electrical or functional impact results from any choice.
M93C46-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8, 64 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M93C46-WMN6TP FAQ
1.How can I place an order for M93C46-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M93C46-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M93C46-WMN6TP reliable?
The price and inventory of M93C46-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M93C46-WMN6TP is usually 5 days.
3.What payment methods are accepted for M93C46-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M93C46-WMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M93C46-WMN6TP?
M93C46-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M93C46-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M93C46-WMN6TP?
For technical support, including M93C46-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M93C46-WMN6TP requirements.
6.How does Aetrix verify that M93C46-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M93C46-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M93C46-WMN6TP meets industry standards.
7.What is the process for return or replacement of M93C46-WMN6TP?
All M93C46-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M93C46-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M93C46-WMN6TP part is unused and in its original packaging.
Return procedure for M93C46-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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