STMicroelectronics M93C56-RMN6TP
- Part No.:
- M93C56-RMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M93C56-RMN6TP.pdf
- Description:
- IC EEPROM 2KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,233
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Product details
Overview
M93C56-RMN6TP from STMicroelectronics is a 2-Kbit serial EEPROM with MICROWIRE™ interface, configurable as 256 × 8-bit or 128 × 16-bit memory, operating from 1.8 V to 5.5 V supply and supporting up to 2 MHz clock frequency. It delivers fast 5 ms byte/page write cycles, 4 million write endurance at 25°C, and 200-year data retention - used for configuration storage in industrial controllers and embedded sensor nodes.
For engineers reviewing the M93C56-RMN6TP datasheet, M93C56-RMN6TP pinout, M93C56-RMN6TP application, or M93C56-RMN6TP equivalent, key selection considerations include its dual x8/x16 organization via ORG pin, READY/BUSY status signaling, enhanced ESD protection (4000 V HBM), SO8N package compatibility, and low-voltage operation down to 1.8 V.
Technical Context
The M93C56-R implements a static CMOS MICROWIRE™-compliant serial bus interface with synchronous clocked read/write operations, supporting instruction-based addressing (9-bit address for x8, 8-bit for x16) and automatic internal erase-before-write. Its ORG pin selects memory width at power-up, and the DU pin is reserved for factory test only.
It features a built-in clock pulse counter to reject corrupted instructions due to noise-induced clock glitches, and uses a POR circuit to prevent spurious writes during power ramp. The Q output provides READY/BUSY status during programming, with Q=0 indicating active write/erase and Q=1 signaling completion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 2048 bits (256 bytes or 128 words) |
| Interface protocol | MICROWIRE™ serial bus (3-wire: S, C, D/Q) |
| Supply voltage range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V, 3.3 V, and 5 V MCUs |
| Max clock frequency | 2 MHz - supports high-speed configuration loading without MCU timing overhead |
| Write cycle time | ≤5 ms per byte or page - reduces firmware wait time during parameter updates |
| Data retention | 200 years at 55°C - ensures long-term reliability in unattended equipment |
| Write endurance | 4 million cycles at 25°C - suitable for frequent calibration or logging applications |
| ESD rating | 4000 V HBM - protects against handling damage in assembly and field service |
Pinout & Package
Package: SO8N (150 mil width, ECOPACK2-compliant).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | 1.8–5.5 V main supply; requires local 10–100 nF decoupling |
| VSS | Ground reference | Return path for all signals; must be low-impedance |
| S | Chip Select | Active-high enable; must be pulled low at power-up to prevent spurious writes |
| C | Serial Clock | Input clock synchronized to MCU SPI-like timing; max 2 MHz |
| D | Serial Data Input | Instruction/address/data input on rising edge of C |
| Q | Serial Data Output / BUSY | Read data output or dynamic READY/BUSY status (Q=0 = busy) |
| ORG | Organization Select | Connect to VSS for x8 mode (256×8), leave open or tie to VCC for x16 mode (128×16) |
| DU | Do Not Use | Factory test pin; may be left floating, tied to VCC, or grounded - no functional role |
Key Features
| Feature | Design Value |
|---|---|
| Dual memory organization | Hardware-selectable x8 or x16 mode via ORG pin - eliminates need for software remapping |
| Ready/Busy signaling | Q pin doubles as status indicator - enables polling instead of fixed delay waits |
| Noise-immune instruction validation | On-chip clock pulse counter aborts misaligned commands - prevents accidental corruption |
| Power-on write protection | Integrated POR circuit blocks all write ops until VCC stabilizes - eliminates external reset logic |
| Enhanced reliability | 4M write cycles + 200-year retention - validated for industrial lifetime requirements |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) |
|---|---|
Use Scenario: Storing calibrated sensor offsets, I/O mapping, and firmware revision flags in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during boot and runtime reconfiguration. Use Value: Dual x8/x16 organization allows compact storage of mixed 8-bit and 16-bit parameters without external glue logic. | Use Scenario: Retaining seat position memory, mirror angle settings, and lighting profiles across vehicle ignition cycles. IC Role / Device Role / Timing Role: Low-voltage (1.8 V compatible) EEPROM interfaced directly to BCM microcontroller's MICROWIRE™ port. Use Value: 4 million write cycles support daily user adjustments over 10+ years without wear-out risk. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Patch Storage |
Use Scenario: Holding factory-calibrated flow rate coefficients and safety thresholds that must survive power loss and meet regulatory traceability. IC Role / Device Role / Timing Role: Secure, tamper-resistant nonvolatile memory with verified 200-year data retention at 55°C. Use Value: ESD-hardened (4000 V HBM) design withstands clinical environment handling and EMI-rich hospital environments. | Use Scenario: Storing field-deployed firmware patches and tariff tables updated remotely via PLC or RF link. IC Role / Device Role / Timing Role: Serial EEPROM accessed by metering SoC during secure boot and OTA update verification. Use Value: READY/BUSY signaling enables deterministic update timing without fixed delays - critical for time-synchronized grid events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25020B-SSHL-T | SPI interface (4-wire), 2 Kbit, 1.8–5.5 V, no ORG pin - fixed 256×8 organization | Lacks hardware-configurable word width; requires SPI-capable host, not MICROWIRE™-only controllers | Select when host MCU lacks MICROWIRE™ peripheral but supports SPI, and x16 mode is unnecessary |
| M93C56-WMN6TP | Same pinout and function, but 2.5–5.5 V supply range - excludes 1.8 V operation | Not suitable for ultra-low-voltage systems (e.g., battery-powered sensors below 2.5 V) | Select only if system VCC is guaranteed ≥2.5 V and legacy compatibility with older W-series designs is required |
Compared with AT25020B-SSHL-T and M93C56-WMN6TP, the M93C56-RMN6TP uniquely supports true 1.8 V operation and hardware-selectable memory width - making it the only choice for mixed-voltage industrial designs requiring flexible data packing without software overhead.
Availability
M93C56-RMN6TP is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, medical device calibration, and smart metering applications requiring stable component supply, long-lifecycle assurance, and RoHS-compliant packaging.
Supply support for M93C56-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M93Cxx series targets cost-sensitive, space-constrained embedded systems needing reliable, low-pin-count serial EEPROM - optimized for robustness in harsh environments and seamless integration with legacy MICROWIRE™-based microcontrollers.
FAQ
What is the function of the DU pin on M93C56-RMN6TP?
The DU (Do Not Use) pin is reserved exclusively for STMicroelectronics factory test sequences and has no functional role in normal operation. It may be left unconnected, tied to VCC, or grounded - none of these choices affect device behavior, reliability, or timing. It must never be driven by external logic.
How does the ORG pin affect memory access timing and address decoding?
The ORG pin sets memory width at power-up and determines address bit count: when ORG = VSS, the device uses 9-bit addresses (x8 mode); when ORG = VCC or floating, it uses 8-bit addresses (x16 mode). This changes instruction length (e.g., WRITE requires 20 vs. 27 clock cycles) and must be matched in host firmware - no runtime reconfiguration is possible.
Can M93C56-RMN6TP be used with an SPI master without modification?
No - M93C56-RMN6TP uses MICROWIRE™ (3-wire, half-duplex, shared D/Q line), not SPI (4-wire, full-duplex, separate MOSI/MISO). While timing overlaps exist, SPI masters cannot natively generate valid MICROWIRE™ start bits or handle the READY/BUSY-driven Q pin behavior. Dedicated MICROWIRE™ or bit-banged GPIO control is required.
Is the 200-year data retention specification validated per JEDEC JESD22-A117?
Yes - STMicroelectronics validates the 200-year retention claim using accelerated testing per JESD22-A117 (high-temperature data retention), extrapolated from measurements at 55°C and confirmed through qualification per AEC-Q100 for automotive-grade variants. The value applies to data stored at ≤55°C ambient and reflects worst-case cell degradation modeling.
M93C56-RMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8, 128 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M93C56-RMN6TP FAQ
1.How can I place an order for M93C56-RMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M93C56-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M93C56-RMN6TP reliable?
The price and inventory of M93C56-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M93C56-RMN6TP is usually 5 days.
3.What payment methods are accepted for M93C56-RMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M93C56-RMN6TP transactions.
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4.How is shipping managed for M93C56-RMN6TP?
M93C56-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M93C56-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M93C56-RMN6TP?
For technical support, including M93C56-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M93C56-RMN6TP requirements.
6.How does Aetrix verify that M93C56-RMN6TP is sourced from the original manufacturer or authorized distributors?
All M93C56-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M93C56-RMN6TP meets industry standards.
7.What is the process for return or replacement of M93C56-RMN6TP?
All M93C56-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M93C56-RMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M93C56-RMN6TP part is unused and in its original packaging.
Return procedure for M93C56-RMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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