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STMicroelectronics M95010-WDW6TP
- Part No.:
- M95010-WDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95010-WDW6TP.pdf
- Description:
- IC EEPROM 1KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:12,105
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Product details
Overview
M95010-WDW6TP from STMicroelectronics is a 1-Kbit (128-byte) serial SPI bus EEPROM organized as 128 × 8 bits, operating from 2.5 V to 5.5 V supply, featuring 16-byte page write capability, 5 ms max write time, and hardware/software write protection for quarter/half/entire memory array. It is used in industrial control modules for parameter storage and calibration data retention.
For engineers reviewing the M95010-WDW6TP datasheet, M95010-WDW6TP pinout, M95010-WDW6TP application, or M95010-WDW6TP equivalent, key selection criteria include VCC range compatibility (2.5–5.5 V), SO8N ECOPACK2 packaging, SPI mode support (CPOL=0/1, CPHA=0/1), ECC-enabled read reliability, and identification-page lockability in higher-density variants.
Technical Context
This device implements a standard SPI interface with dual-phase clocking (CPOL/CPHA configurable), supporting both CPOL=0, CPHA=0 and CPOL=1, CPHA=1 modes. Data is latched on rising C edge (D input) and output on falling C edge (Q output), enabling deterministic timing alignment with MCU peripherals.
The internal architecture includes an ECC x1 logic block per byte, correcting single-bit errors during read operations, and a status register with non-volatile BP1/BP0 bits controlling software-based write protection zones. The HOLD pin enables communication pause without chip deselection, preserving instruction state across transient host interruptions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Kbit (128 × 8 bits); sufficient for firmware configuration flags, sensor calibration coefficients, or small boot parameters in space-constrained designs. |
| Page size | 16 bytes; defines minimum write granularity - reduces bus overhead vs. byte-write-only devices and enables efficient bulk updates. |
| Write time | ≤5 ms per byte or page; enables fast field-updatable settings without blocking host MCU for extended periods. |
| VCC range | 2.5 V to 5.5 V; supports direct interfacing with 3.3 V and 5 V logic systems without level-shifting circuitry. |
| Operating temp | −40 °C to +85 °C; qualified for industrial ambient environments including motor drives, PLC I/O modules, and HVAC controllers. |
| Data retention | >200 years; ensures long-term validity of stored calibration or security keys without refresh cycles. |
| Endurance | >4 million write cycles; supports frequent runtime logging or adaptive tuning in closed-loop control applications. |
Pinout & Package
Supplied in RoHS-compliant, halogen-free SO8N (ECOPACK2) package (150 mil width), with 8-pin DIP-compatible footprint and standard pin 1 marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable signal; falling edge initiates instruction decoding and must precede all valid SPI transactions. |
| C | Serial clock | Master-generated clock; rising edge latches input (D), falling edge outputs data (Q); supports up to 20 MHz operation. |
| D | Serial data input | Input for instruction codes, addresses, and write data; MSB-first protocol compliant with standard SPI peripherals. |
| Q | Serial data output | Output for read data and status register contents; high-impedance when S is high or HOLD is active. |
| W | Write protect | Hardware-level write disable; driven low to block all WRITE/WRSR commands regardless of WEL or BP bit state. |
| HOLD | Communication hold | Pauses ongoing SPI transfer without resetting internal state; requires S low and C low for valid assertion/deassertion. |
| VCC | Supply voltage | 2.5–5.5 V power rail; decoupling capacitor (10–100 nF) required near pins to maintain stability during write cycles. |
| VSS | Ground reference | Common return path for all signals and internal logic; must be low-impedance and tied directly to system ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| ECC x1 per byte | Corrects single-bit read errors transparently - improves data integrity in electrically noisy industrial environments without software overhead. |
| Flexible write protection | Software-configurable BP1/BP0 bits enable selective locking of upper quarter/half or full memory array, preventing accidental overwrites of critical firmware data. |
| HOLD functionality | Enables host MCU to suspend EEPROM communication mid-transaction (e.g., during interrupt servicing) and resume without reinitializing the command sequence. |
| Power-on reset (POR) | Prevents spurious writes during power ramp-up by holding device in standby until VCC exceeds internal threshold (VRES), ensuring deterministic startup behavior. |
| SO8N ECOPACK2 package | Industry-standard 8-lead SOIC footprint with enhanced thermal and environmental compliance - simplifies PCB layout and qualifies for industrial reflow profiles. |
Applications
| Industrial Sensor Calibration | PLC Configuration Storage |
|---|---|
Use Scenario: Storing temperature, offset, and gain coefficients for analog sensor front-ends in factory-floor instrumentation. IC Role / Device Role / Timing Role: Non-volatile parameter register accessed via SPI during sensor initialization or recalibration routines. Use Value: Enables field-adjustable calibration without firmware update; ECC ensures coefficient integrity despite EMI exposure near motors or drives. | Use Scenario: Retaining I/O mapping, scan cycle timing, and alarm thresholds in programmable logic controller modules. IC Role / Device Role / Timing Role: Persistent configuration store updated only during commissioning or maintenance - not during runtime scanning. Use Value: Hardware write protection (W pin + BP bits) prevents corruption during brown-out events or firmware glitches in mission-critical control loops. |
| Smart Meter Firmware Flags | Medical Device Settings Backup |
Use Scenario: Holding tariff schedules, pulse constants, and tamper-detection flags in utility smart meters with long deployment lifetimes. IC Role / Device Role / Timing Role: Low-power, infrequently written configuration vault accessed during meter boot or firmware upgrade handshake. Use Value: >200-year data retention guarantees flag validity across entire product lifecycle; 4M-cycle endurance supports periodic firmware revision tracking. | Use Scenario: Backing up user-selectable therapy parameters (e.g., infusion rate limits, alarm thresholds) in portable infusion pumps. IC Role / Device Role / Timing Role: Safety-critical non-volatile memory isolated from main MCU flash - updated only after clinical validation and confirmation. Use Value: Dual protection (hardware W pin + software BP bits) enforces write-locking post-configuration, satisfying IEC 62304 traceability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25010B-SSHL-T | 1-Kbit SPI EEPROM, 1.8–5.5 V VCC, 10 MHz max clock, no HOLD pin, no ECC | Lacks HOLD functionality and error correction; suitable for cost-sensitive, low-noise consumer applications only | Select if board space allows TSSOP8 and system does not require communication pause or ECC robustness |
| BR24G01FJ-WE2 | 1-Kbit I²C EEPROM, 1.7–5.5 V, 400 kHz/1 MHz, built-in write protect, no SPI interface | Uses I²C instead of SPI - incompatible bus protocol; requires different MCU peripheral and driver stack | Choose only when existing design uses I²C infrastructure and SPI pins are unavailable or contested |
Compared with AT25010B-SSHL-T and BR24G01FJ-WE2, M95010-WDW6TP uniquely combines SPI compatibility, HOLD pin for deterministic interrupt handling, and per-byte ECC - making it optimal for industrial systems where bus reliability, timing control, and data integrity are jointly critical.
Availability
M95010-WDW6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, PLC configuration storage, and smart meter firmware flag retention requiring stable component supply across multi-year production programs.
Supply support for M95010-WDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
M95010-WDW6TP belongs to the M950x0-W series of SPI EEPROMs engineered specifically for robust, low-power, and noise-resilient non-volatile storage in industrial control and instrumentation systems.
FAQ
What SPI modes does M95010-WDW6TP support?
M95010-WDW6TP supports two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C (D input) and output on the falling edge (Q output). The difference lies only in idle clock polarity - C remains low in the first mode and high in the second - allowing seamless integration with most MCU SPI peripherals without protocol translation.
How does the HOLD function interact with chip select (S)?
HOLD requires the device to be selected (S low) before activation. When HOLD goes low while C is low, communication pauses immediately: Q enters high-impedance, and D/C become don't-care. The internal state (address counter, instruction phase) is preserved. Resuming requires HOLD high while C remains low - no new S falling edge is needed, enabling atomic interruption and resumption of multi-byte transfers.
Can the write protect (W) pin override software block protection?
Yes. Driving W low disables all write operations - including WRITE, WRSR, WRID, and LID - regardless of WEL latch state or BP1/BP0 configuration. This hardware lock provides fail-safe protection against firmware bugs or voltage transients that might corrupt software protection bits, and is mandatory for safety-critical parameter storage.
Is the identification page available on M95010-WDW6TP?
No. The 16-byte identification page with permanent lock capability (LID instruction) is exclusive to M95040-DF variants. M95010-WDW6TP has only the main 128-byte memory array and standard status register. Its BP1/BP0 bits can still protect the upper quarter (60h–7Fh) or half (40h–7Fh) of that array, but no separate ID page exists.
M95010-WDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95010-WDW6TP FAQ
1.How can I place an order for M95010-WDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95010-WDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95010-WDW6TP reliable?
The price and inventory of M95010-WDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95010-WDW6TP is usually 5 days.
3.What payment methods are accepted for M95010-WDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95010-WDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95010-WDW6TP?
M95010-WDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95010-WDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95010-WDW6TP?
For technical support, including M95010-WDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95010-WDW6TP requirements.
6.How does Aetrix verify that M95010-WDW6TP is sourced from the original manufacturer or authorized distributors?
All M95010-WDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95010-WDW6TP meets industry standards.
7.What is the process for return or replacement of M95010-WDW6TP?
All M95010-WDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95010-WDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95010-WDW6TP part is unused and in its original packaging.
Return procedure for M95010-WDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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