STMicroelectronics M95010-WMN6TP
- Part No.:
- M95010-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95010-WMN6TP.pdf
- Description:
- IC EEPROM 1KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:11,066
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Product details
Overview
M95010-WMN6TP from STMicroelectronics is a 1-Kbit (128-byte) serial SPI bus EEPROM with 16-byte page architecture, 2.5–5.5 V single-supply operation, and industrial temperature range (−40 °C to +85 °C), used for nonvolatile parameter storage in microcontroller-based embedded systems requiring byte- or page-level writes.
For engineers reviewing the M95010-WMN6TP datasheet, M95010-WMN6TP pinout, M95010-WMN6TP application, or M95010-WMN6TP equivalent, key selection criteria include write protect granularity (quarter/half/whole array), ECC-enabled read reliability, 20 MHz max SPI clock support, and ECOPACK2-compliant SO8N/TSSOP8/UFDFPN8 packaging options.
Technical Context
The M95010-WMN6TP implements a standard SPI interface with CPOL=0/CPHA=0 or CPOL=1/CPHA=1 mode compatibility, using dedicated S (chip select), C (clock), D (data in), Q (data out), W (write protect), and HOLD (communication pause) signals. Its internal architecture includes an ECC x1 logic per memory byte, status register with WIP/WEL/BP1/BP0 bits, and high-voltage generator for EEPROM programming.
It supports byte and page write operations (≤5 ms), offers three software-configurable write protection levels via BP1/BP0 bits, and features built-in power-on reset (POR) with VRES threshold monitoring to prevent spurious writes during supply ramp-up or brownout conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Kbit (128 × 8 bits), sufficient for firmware calibration data, device ID, or configuration flags in space-constrained designs. |
| Page size | 16 bytes - defines minimum write granularity and influences buffer sizing in host MCU firmware. |
| Write time | ≤5 ms per byte or page - enables deterministic timing for real-time systems without polling overhead beyond tW. |
| Supply voltage | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V logic domains without level shifting. |
| Max SPI clock | 20 MHz - supports high-throughput parameter updates in fast-boot or diagnostics sequences. |
| Data retention | 200 years - ensures long-term validity of stored settings across product lifecycle without refresh. |
| Endurance | 4 million write cycles - accommodates frequent logging or field-updatable parameters in industrial controllers. |
Pinout & Package
Package: SO8N (ECOPACK2, 150 mil width), RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable signal; falling edge initiates instruction decoding and must precede all valid SPI transactions. |
| C | Serial clock | Timing reference for data latching (rising edge for input, falling edge for output); supports up to 20 MHz. |
| D | Serial data input | Carries instruction codes, addresses, and write data; MSB-first, sampled on rising edge of C. |
| Q | Serial data output | Drives read data and status register contents; high-impedance when deselected or in HOLD state. |
| W | Write protect | Hardware-level lock: low disables all writes regardless of WEL or BP bits, preventing accidental corruption. |
| HOLD | Communication hold | Pauses ongoing SPI transfer without deselecting device; requires S low and C low for valid assertion. |
| VCC | Supply voltage | 2.5–5.5 V power rail; requires local 10–100 nF decoupling capacitor near pins for stable operation. |
| VSS | Ground | Reference for all I/O and internal circuitry; must be low-impedance connection to system ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| ECC x1 per byte | Corrects single-bit errors during read operations, improving data integrity in electrically noisy environments without host-side error handling. |
| Three-tier software write protection | BP1/BP0 bits enable selective locking of upper quarter, upper half, or entire memory array-ideal for safeguarding bootloader or security keys. |
| Hold function with no state loss | Allows MCU to suspend EEPROM communication mid-transaction (e.g., during interrupt servicing) and resume seamlessly without reinitialization. |
| Power-on reset (POR) with VRES threshold | Guarantees WEL=0 and WIP=0 at startup, eliminating risk of unintended writes during power ramp-up or brownout recovery. |
| ECOPACK2 packaging | SO8N, TSSOP8, and UFDFPN8 variants meet RoHS and halogen-free requirements for global industrial and automotive compliance. |
Applications
| Industrial Sensor Calibration | Smart Meter Firmware Storage |
|---|---|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and temperature compensation tables in environmental monitoring nodes. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed during boot and periodic self-test; ECC ensures accuracy of critical calibration values. Use Value: Eliminates need for external checksum validation or redundant storage, reducing BOM count and firmware complexity. | Use Scenario: Retaining tariff schedules, metering logs, and cryptographic keys in utility-grade electricity meters operating over 15+ years. IC Role / Device Role / Timing Role: Secure, long-life configuration memory with hardware write protect (W pin) to prevent tampering during field deployment. Use Value: 200-year data retention and 4M-cycle endurance ensure reliable operation across full product lifetime without maintenance. |
| Automotive Body Control Module | Medical Device Configuration |
Use Scenario: Saving user preferences (mirror position, seat settings) and diagnostic fault codes in 12 V automotive body control units. IC Role / Device Role / Timing Role: SPI EEPROM interfaced directly to 3.3 V MCU; operates across −40 °C to +85 °C ambient with no derating. Use Value: Wide 2.5–5.5 V supply range tolerates battery voltage fluctuations (e.g., cold-crank dips to ~6 V or alternator surges). | Use Scenario: Storing FDA-mandated device serial numbers, calibration history, and usage counters in portable infusion pumps and diagnostic tools. IC Role / Device Role / Timing Role: Tamper-resistant configuration memory with page-lock capability to preserve audit trail integrity. Use Value: Identification page (available in DF variant) not applicable here, but BP1/BP0 locking prevents unauthorized overwrite of regulatory-critical fields. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25010B-SSHL-T (Microchip) | 1 Kbit SPI EEPROM; 1.8–5.5 V supply; no ECC; 1 million write cycles; SO8 package only. | Lacks ECC and extended endurance; suitable where cost sensitivity outweighs long-term reliability needs. | Select if legacy design uses AT25xxx footprint and ECC is not required for target application. |
| BR24G01FJ-3GE2 (ROHM) | 1 Kbit SPI EEPROM; 1.7–5.5 V supply; 1 million write cycles; built-in write protect pin; no identification page. | Lower endurance and no ECC; includes automatic address increment feature not present in M95010. | Prefer for ultra-low-voltage (1.7 V) systems where BR24G01's auto-increment simplifies sequential reads. |
Compared with AT25010B and BR24G01FJ, the M95010-WMN6TP provides superior data integrity (ECC), longer endurance (4M vs. 1M cycles), and finer write protection granularity-making it optimal for mission-critical industrial and medical applications demanding verified reliability.
Availability
M95010-WMN6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, smart meter firmware storage, and automotive body control modules requiring stable component supply, long-term obsolescence management, and RoHS-compliant sourcing.
Supply support for M95010-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and memory solutions for industrial, automotive, and consumer markets.
The M950x0 series targets cost-sensitive, high-reliability embedded systems needing robust, SPI-compatible EEPROM with enhanced data integrity and flexible write protection-optimized for space-constrained PCBs and extended operational lifetimes.
FAQ
Does M95010-WMN6TP support dual- or quad-SPI modes?
No. The M95010-WMN6TP supports only standard single-data-line SPI (mode 0 and mode 3), with dedicated D (input) and Q (output) pins. It does not implement dual-output (D/Q multiplexed) or quad-SPI protocols, nor does its instruction set include fast-read or quad-write commands.
Can the HOLD pin be used while the device is not selected (S high)?
No. The HOLD function requires the device to be selected (S low) to activate. When S is high, the device is in standby mode and ignores HOLD transitions; asserting HOLD alone has no effect unless S is simultaneously low and C is low at the moment of assertion.
What happens if W is held low while issuing a WREN instruction?
Write operations remain disabled regardless of WREN execution. The W (write protect) pin overrides software write enable: even with WEL=1 and BP bits cleared, all WRITE, WRSR, WRID, and LID instructions are ignored while W is low-providing fail-safe hardware-level protection.
Is the identification page available in M95010-WMN6TP?
No. The identification page (16-byte read/write/lockable area) is exclusive to the M95040-DF variant. The M95010-WMN6TP has only the main 128-byte memory array and standard status register; RDID, WRID, RDLS, and LID instructions are not supported and will be ignored.
M95010-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95010-WMN6TP FAQ
1.How can I place an order for M95010-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95010-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95010-WMN6TP reliable?
The price and inventory of M95010-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95010-WMN6TP is usually 5 days.
3.What payment methods are accepted for M95010-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95010-WMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95010-WMN6TP?
M95010-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95010-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95010-WMN6TP?
For technical support, including M95010-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95010-WMN6TP requirements.
6.How does Aetrix verify that M95010-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M95010-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95010-WMN6TP meets industry standards.
7.What is the process for return or replacement of M95010-WMN6TP?
All M95010-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95010-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95010-WMN6TP part is unused and in its original packaging.
Return procedure for M95010-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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