STMicroelectronics M95020-DRMF3TG/K

Overview

M95020-DRMF3TG/K from STMicroelectronics is an automotive-grade 2-Kbit serial SPI EEPROM with AEC-Q100 Grade 0 qualification, operating up to 145 °C and supporting 20 MHz clock at V_CC ≥ 4.5 V. It features 256 × 8-bit memory organized in 16-byte pages, embedded ECC for data integrity, and a dedicated 16-byte lockable Identification Page used for device ID storage or application-critical parameters in automotive body control modules.

For engineers reviewing the M95020-DRMF3TG/K datasheet, M95020-DRMF3TG/K pinout, M95020-DRMF3TG/K application, or M95020-DRMF3TG/K equivalent, key selection criteria include extended temperature operation (up to 145 °C), block-level write protection (1/4, 1/2, or full memory), fast page write time (≤4 ms), and compatibility with CPOL=0/CPHA=0 and CPOL=1/CPHA=1 SPI modes.

Technical Context

This SPI EEPROM implements a synchronous serial interface with Schmitt-trigger inputs for noise immunity and supports dual SPI modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1) to match diverse microcontroller peripherals. Its internal logic includes a status register with WIP and WEL flags, non-volatile BP1/BP0 bits for configurable block protection, and dedicated instruction decoding for READ, WRITE, RDSR, WRSR, RDID, WRID, and LID operations.

The device integrates error correction code (ECC x1) across the main memory array to detect and correct single-bit errors, enhancing reliability in harsh automotive environments. The separate 16-byte Identification Page is independently addressable and lockable-once locked via LID instruction, it becomes permanently read-only, safeguarding calibration data or firmware identifiers.

Key Specifications

Pinout & Package

Package: TSSOP8 (DW), 3 × 4.4 mm, 0.65 mm pitch, RoHS-compliant and halogen-free (ECOPACK2®).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Compared with AT25DF021A-SSH-T and BR24G02FJ-3GE2, the M95020-DRMF3TG/K uniquely delivers AEC-Q100 Grade 0 qualification, ECC-protected memory, and a lockable Identification Page-all within a SPI-compatible 2-Kbit footprint-making it the sole fit for safety-critical, high-temperature automotive parameter storage.

Availability

M95020-DRMF3TG/K is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, body control modules, and electric power steering systems requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for M95020-DRMF3TG/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

The M95020 series belongs to ST's automotive EEPROM product line, engineered specifically for mission-critical data retention in extreme thermal environments-including under-hood, transmission, and brake control applications-where reliability and longevity are non-negotiable.

FAQ

What is the function of the HOLD pin, and how does it differ from Chip Select (S)?

The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state-allowing the host MCU to service higher-priority interrupts while preserving the exact byte boundary and clock phase. In contrast, driving Chip Select (S) high terminates the transaction, forces Q into high-impedance, and resets the command decoder. HOLD requires S low and C low to activate, whereas S controls overall device selection and command acceptance.

How is write protection implemented, and can it be overridden in-system?

Write protection is enforced through two independent mechanisms: hardware (W pin disables Status Register writes) and software (BP1/BP0 bits in Status Register define protected memory blocks). Once BP1/BP0 are set via WRSR, they remain non-volatile until cleared by another WRSR with WREN enabled. The W pin cannot override BP bits but prevents accidental WRSR execution. No mechanism allows overriding protection without explicit host MCU action-ensuring tamper-resistant configuration storage.

Does the Identification Page support partial writes, and what happens after executing LID?

The Identification Page supports byte- and page-level writes like the main array, but only before locking. After executing the Lock Identification Page (LID) instruction, the entire 16-byte page becomes permanently read-only: subsequent WRID attempts return no error but have no effect, and RDID continues to output stored data. The lock is irreversible and does not affect main memory access-enabling secure separation of immutable calibration data from dynamic configuration.

What SPI modes are supported, and how does the device handle clock polarity mismatches?

The M95020-DRMF3TG/K supports only CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes-both sampling input on C rising edge and outputting on C falling edge. It does not support CPOL=0/CPHA=1 or CPOL=1/CPHA=0. If the host MCU configures an unsupported mode, data will be misaligned or commands rejected due to incorrect edge timing; no automatic detection or fallback occurs. Designers must verify MCU SPI peripheral configuration matches one of the two supported modes.