STMicroelectronics M95020-WMN6TP
- Part No.:
- M95020-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95020-WMN6TP.pdf
- Description:
- IC EEPROM 2KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:11,134
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95020-WMN6TP from STMicroelectronics is a 2-Kbit (256-byte) serial SPI bus EEPROM organized as 256 × 8 bits, operating from 2.5 V to 5.5 V supply voltage with 20 MHz max clock frequency. It features hardware write protection (quarter/half/whole array), 16-byte page write capability with ≤5 ms write time, and integrated ECC for single-bit error correction during read operations. Used in industrial control modules for parameter storage and calibration data retention.
For engineers reviewing the M95020-WMN6TP datasheet, M95020-WMN6TP pinout, M95020-WMN6TP application, or M95020-WMN6TP equivalent, key selection criteria include supply voltage range compatibility (2.5–5.5 V), SPI mode support (CPOL=0/1, CPHA=0/1), write-protect granularity, identification page availability, and ECOPACK2-compliant SO8N packaging.
Technical Context
The M95020-WMN6TP implements a synchronous serial interface compliant with SPI protocol modes (CPOL, CPHA) = (0,0) and (1,1), where data is latched on rising clock edge (D input) and output on falling edge (Q output). Its internal architecture includes a status register with non-volatile BP1/BP0 bits controlling software block protection, a write enable latch (WEL), and a write-in-progress (WIP) flag.
It integrates an on-chip high-voltage generator and sequencer for EEPROM programming, supports HOLD signal for transaction pausing without chip deselection, and provides built-in power-on reset (POR) with VRES threshold monitoring. The device delivers >4 million write cycles and >200-year data retention at +85 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 2 Kbit (256 × 8 bits) - fixed address space usable for configuration storage without external addressing logic |
| Supply voltage | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V microcontroller I/O domains without level shifting |
| Max clock frequency | 20 MHz - enables fast parameter loading in boot-time initialization sequences |
| Write time | ≤5 ms per byte or page - supports deterministic timing for firmware update rollback mechanisms |
| Data retention | >200 years at +85 °C - ensures long-term reliability in unattended industrial deployments |
| Write endurance | >4 million cycles - sufficient for daily recalibration logging over 10+ years |
| ECC support | Single-bit error correction per byte - improves read reliability in electrically noisy factory environments |
Pinout & Package
Package: SO8N (ECOPACK2), 150 mil width, RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselects device and places Q in high-impedance state |
| C | Serial clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q); supports CPOL=0/1 |
| D | Serial data input | MSB-first input for instructions, addresses, and write data; sampled on rising edge of C |
| Q | Serial data output | MSB-first output for READ/RDSR responses; high-impedance during HOLD or when S is high |
| W | Write protect | Hardware-level write disable when low; overrides software BP bits and WEL state; must not float |
| HOLD | Communication hold | Pauses ongoing SPI transfer without resetting internal state; requires S low and C low for activation/deactivation |
| VCC | Supply voltage | 2.5–5.5 V power rail; requires local 10–100 nF decoupling capacitor near pins |
| VSS | Ground | Reference for all signals and VCC; must be low-impedance connection shared with MCU ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Page write (16 bytes) | Reduces firmware update time by 16× vs. byte-write; aligns with typical MCU cache line sizes |
| Block protection (BP1/BP0) | Configurable quarter/half/full memory lock via WRSR - prevents accidental overwrite of critical calibration tables |
| HOLD functionality | Enables multi-device SPI arbitration without interrupting internal state - essential for real-time PLC scan cycles |
| Enhanced ESD protection | Withstands >4 kV HBM - reduces field failure risk in handling-sensitive industrial assembly lines |
| ECOPACK2 packaging | SO8N footprint with lead-free, halogen-free materials - meets EU RoHS and REACH compliance requirements |
Applications
| Industrial Sensor Calibration | Smart Meter Firmware Storage |
|---|---|
|
Use Scenario: Storing temperature compensation coefficients and sensor offset values during factory calibration of pressure transmitters. IC Role / Device Role / Timing Role: Non-volatile parameter storage accessed during power-up initialization and runtime correction routines. Use Value: Enables field-replaceable sensor heads with pre-loaded calibration data, eliminating need for re-calibration after module swap. |
Use Scenario: Holding firmware patch metadata, secure boot keys, and tariff schedule tables in utility-grade electricity meters. IC Role / Device Role / Timing Role: Secure, tamper-resistant configuration store accessed only by trusted bootloader during cold start. Use Value: Supports remote firmware updates with rollback protection and cryptographic key persistence across power cycles. |
| PLC I/O Module Configuration | Medical Device Parameter Archiving |
|
Use Scenario: Retaining channel-specific scaling factors, alarm thresholds, and input filter settings in modular programmable logic controllers. IC Role / Device Role / Timing Role: SPI-configurable memory mapped into controller's peripheral address space for dynamic reconfiguration. Use Value: Allows hot-swappable I/O modules to retain user-defined behavior without host-side configuration reload. |
Use Scenario: Logging device serial number, manufacturing date, calibration history, and usage counters in portable diagnostic equipment. IC Role / Device Role / Timing Role: Audit-trail storage with ECC-protected reads to ensure regulatory compliance data integrity. Use Value: Meets FDA 21 CFR Part 11 requirements for electronic record authenticity and long-term readability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF021A-SSH-T | 2 Mbit density, quad-SPI interface, 3.0–3.6 V only, no HOLD pin | Higher capacity but narrower voltage range; lacks HOLD for real-time pause capability | Select when larger firmware image storage is needed and system operates strictly at 3.3 V |
| BR24G256FJ-WE2 | I²C interface, 256 Kbit, 1.7–5.5 V, no hardware W pin, no identification page | Slower interface (max 1 MHz), no hardware write protect, incompatible bus protocol | Select only if existing design uses I²C infrastructure and SPI is unavailable |
Compared with AT25DF021A-SSH-T and BR24G256FJ-WE2, M95020-WMN6TP offers optimal balance of SPI compatibility, 2.5–5.5 V operation, hardware write protection, and HOLD functionality - making it preferred for industrial controllers requiring deterministic, robust, and voltage-flexible configuration storage.
Availability
M95020-WMN6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, smart meter firmware storage, PLC I/O module configuration, and medical device parameter archiving requiring stable component supply across extended product lifecycles.
Supply support for M95020-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory products for industrial, automotive, and consumer markets.
M95020-WMN6TP belongs to the M950x0-W series of SPI EEPROMs engineered for reliable, low-power, voltage-flexible non-volatile storage in harsh industrial environments with stringent longevity and data integrity requirements.
FAQ
What SPI modes does M95020-WMN6TP support?
M95020-WMN6TP supports two SPI modes: (CPOL = 0, CPHA = 0) and (CPOL = 1, CPHA = 1). In both, data is latched on the rising edge of the serial clock (C) at the D input and output on the falling edge at Q. The difference lies only in idle clock polarity - C remains low in mode 0,0 and high in mode 1,1 - enabling interoperability with diverse MCU SPI peripherals without protocol translation.
How does hardware write protection (W pin) interact with software block protection (BP bits)?
The W pin provides unconditional hardware-level write disable when driven low, overriding all software protections including BP1/BP0 settings and the WEL bit. When W is high, software block protection becomes active and governs which memory regions accept WRITE or WRSR commands. This dual-layer scheme ensures fail-safe protection: hardware guard against system-level faults, software guard for application-level access control.
Can the HOLD function be used during an active write cycle?
No - HOLD is ignored during internal write cycles (tW). The device will complete the ongoing byte or page write before responding to HOLD assertion. This ensures data integrity: once a write command is accepted and latched, it proceeds to completion regardless of external hold requests. HOLD is only effective during instruction transmission, address/data shifting, or idle states between transactions.
Is the identification page available on M95020-WMN6TP?
No - the identification page (16 bytes, lockable read-only) is exclusive to M95040-DF order codes. M95020-WMN6TP is part of the M950x0-W family and does not include this feature. Its memory map consists solely of the main 256-byte array with BP1/BP0-controlled protection zones, and no dedicated ID page or LID/WRID/RDID instructions.
M95020-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95020-WMN6TP FAQ
1.How can I place an order for M95020-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95020-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95020-WMN6TP reliable?
The price and inventory of M95020-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95020-WMN6TP is usually 5 days.
3.What payment methods are accepted for M95020-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95020-WMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95020-WMN6TP?
M95020-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95020-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95020-WMN6TP?
For technical support, including M95020-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95020-WMN6TP requirements.
6.How does Aetrix verify that M95020-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M95020-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95020-WMN6TP meets industry standards.
7.What is the process for return or replacement of M95020-WMN6TP?
All M95020-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95020-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95020-WMN6TP part is unused and in its original packaging.
Return procedure for M95020-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95020-WMN6TP Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
