My Inquiry
My Account
STMicroelectronics M95040-DRDW8TP/K
- Part No.:
- M95040-DRDW8TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95040-DRDW8TP/K.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,202
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95040-DRDW8TP/K from STMicroelectronics is a 4-Kbit serial SPI EEPROM with 512 × 8-bit memory array, 16-byte page size, and extended operation up to 105 °C at VCC = 1.7–5.5 V. It features block-wise write protection (1/4, 1/2, or full memory), an additional lockable 16-byte identification page, and Schmitt-trigger inputs for noise immunity - deployed in automotive body control modules for storing calibration data and fault logs.
For engineers reviewing the M95040-DRDW8TP/K datasheet, M95040-DRDW8TP/K pinout, M95040-DRDW8TP/K application, or M95040-DRDW8TP/K equivalent, key selection criteria include guaranteed 105 °C endurance (900 k write cycles), embedded ECC logic for enhanced data integrity, and support for dual SPI modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1) in space-constrained industrial controllers.
Technical Context
This SPI EEPROM implements a true EEPROM cell structure with byte-alterable capability and integrated Error Correction Code (ECC x 1) logic that detects and corrects single-bit errors during read operations. Its status register (WIP/WEL/BP1/BP0) enables precise control over write enable state and non-volatile block protection configuration.
The device supports two standard SPI clock polarities and phases (CPOL=0, CPHA=0 and CPOL=1, CPHA=1), with data latched on the rising edge of C and output shifted on the falling edge. Hold mode pauses communication without resetting the internal state, and the identification page provides factory-programmed ST device codes plus user-writable, lockable application parameters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 bytes), organized as 32 pages × 16 bytes - enables efficient firmware parameter storage with minimal bus overhead. |
| Max clock frequency | 20 MHz at VCC ≥ 4.5 V - supports high-throughput configuration updates in real-time control loops. |
| Write endurance | 900 k cycles at 105 °C - ensures reliable logging in under-hood automotive environments over full vehicle lifetime. |
| Data retention | >50 years at 105 °C - guarantees long-term validity of safety-critical calibration data without refresh. |
| Operating temperature | −40 °C to +105 °C - qualified per AEC-Q100 Grade 2 for engine bay and powertrain applications. |
| Supply voltage | 1.7 V to 5.5 V - interoperable with 1.8 V, 3.3 V, and 5 V microcontroller I/O domains without level shifters. |
| ESD protection | 4000 V HBM - withstands handling and board-level transients in automated manufacturing and field service. |
Pinout & Package
Package: TSSOP8 (DW), 169 mil width, RoHS-compliant and halogen-free (ECOPACK2®).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S (Chip Select) | Active-low device enable | Edge- and level-sensitive; must transition high→low to initiate command decoding - prevents spurious writes during power-up. |
| C (Serial Clock) | Synchronization input | Drives timing for all SPI transfers; supports dual modes (CPOL/CPHA); rising edge latches input, falling edge outputs data. |
| D (Serial Data Input) | Command/address/data input | Accepts instruction byte, address, and payload; MSB-first; sampled on rising edge of C. |
| Q (Serial Data Output) | Read data output | Outputs memory contents or status bits; high-impedance when deselected or in Hold mode; data valid after falling edge of C. |
| W (Write Protect) | Status register protection | Hardware pin that disables writes to BP1/BP0 and WEL bits - adds physical layer security against accidental reconfiguration. |
| HOLD | Communication pause control | Halts ongoing SPI transfer without deselecting device; requires S low and C low to activate - preserves state during CPU interrupt servicing. |
| VCC | Power supply | 1.7–5.5 V operation enables direct interface with mixed-voltage SoCs and reduces need for auxiliary regulators. |
| VSS | Ground reference | Common return for all signals and internal logic - must be low-impedance to maintain noise margin for Schmitt-trigger inputs. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Single-bit error correction on every read - eliminates silent data corruption in safety-critical parameter storage. |
| Lockable identification page | 16-byte dedicated area with RDID/WRID/LID instructions - allows permanent locking of calibrated sensor offsets or cryptographic keys. |
| Multi-level write protection | BP1/BP0 bits configure 1/4, 1/2, or full memory block lock - enables hierarchical access control for boot code vs. runtime variables. |
| Short write cycle time | ≤4 ms for byte or page write - minimizes bus occupation time and improves system responsiveness during configuration updates. |
| Schmitt-trigger inputs | Hysteresis on S, C, D, HOLD, W - rejects noise spikes up to 300 mV on PCB traces in electrically noisy automotive environments. |
Applications
| Automotive Body Control Unit | Industrial PLC Configuration Storage |
|---|---|
|
Use Scenario: Storing door module calibration values, seat position presets, and fault history across vehicle lifetime. IC Role / Device Role / Timing Role: Non-volatile parameter repository with AEC-Q100 Grade 2 qualification and 105 °C operation. Use Value: Eliminates need for external backup capacitors or battery-backed SRAM while guaranteeing 50+ year data retention at under-hood temperatures. |
Use Scenario: Holding I/O mapping tables, PID tuning constants, and firmware update flags in modular automation controllers. IC Role / Device Role / Timing Role: SPI-configurable persistent memory interfaced directly to ARM Cortex-M7 MCU with no glue logic. Use Value: Enables field-upgradable logic without requiring full flash reprogramming - reduces downtime during maintenance windows. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Parameters |
|
Use Scenario: Securing drug delivery rate limits, dose history, and sensor offset compensation in Class IIa medical devices. IC Role / Device Role / Timing Role: Tamper-resistant storage with lockable ID page for regulatory audit trails and cryptographic key material. Use Value: Meets IEC 62304 software lifecycle requirements via hardware-enforced write protection and ECC-verified reads. |
Use Scenario: Retaining tariff schedules, metering calibration coefficients, and tamper-event timestamps in ANSI C12.22-compliant meters. IC Role / Device Role / Timing Role: High-reliability EEPROM operating continuously at 85 °C inside sealed outdoor enclosures. Use Value: Delivers 1.2 million write cycles at 85 °C - exceeds ANSI 12.22 minimum endurance for 20-year field deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25040B-SSHL-T (Microchip) | Same 4-Kbit density and SO8/TSSOP8 packages; lacks identification page and ECC; max temp 85 °C. | Not qualified for under-hood automotive use; suitable for consumer-grade industrial controls. | Select only if AEC-Q100 Grade 2 and 105 °C operation are not required. |
| BR24G04FJ-3GE2 (ROHM) | 4-Kbit SPI EEPROM with 105 °C rating; no identification page; write endurance 1M cycles at 25 °C but unspecified at 105 °C. | Lacks lockable ID page for secure key storage; no published ECC implementation. | Prefer when cost sensitivity outweighs need for embedded ECC and factory-locked device ID. |
Compared with AT25040B-SSHL-T and BR24G04FJ-3GE2, the M95040-DRDW8TP/K uniquely combines AEC-Q100 Grade 2 qualification, 105 °C endurance specification, embedded ECC, and a lockable identification page - making it the only option for safety-critical automotive and medical applications requiring traceable, tamper-resistant parameter storage.
Availability
M95040-DRDW8TP/K is available at Aetrix Electronics and suitable for automotive body control units, industrial PLCs, medical infusion pumps, and smart energy meters requiring stable component supply across extended temperature ranges and multi-decade data retention.
Supply support for M95040-DRDW8TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management solutions, with broad analog, MCU, and memory portfolios.
The M95040-DRDW8TP/K belongs to ST's automotive-qualified serial EEPROM product line, designed specifically for robust, long-life non-volatile storage in harsh environments where reliability and data integrity are mission-critical.
FAQ
What is the function of the HOLD pin on the M95040-DRDW8TP/K?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. Activation requires Chip Select (S) low and Serial Clock (C) low; during Hold, Q goes high-impedance and D/C are ignored. This allows the host MCU to service interrupts or perform other tasks while preserving the exact point in the SPI transaction, resuming seamlessly upon deassertion.
How does the identification page differ from main memory in the M95040-DRDW8TP/K?
The identification page is a dedicated 16-byte area separate from the main 512-byte array. Bytes 0–2 contain factory-programmed ST device codes (20h/00h/09h); remaining bytes are user-writable for application-specific data. Unlike main memory, this page supports LID (Lock Identification) instruction to permanently disable further writes - enabling secure storage of calibration keys or cryptographic material.
Can the M95040-DRDW8TP/K operate reliably at 1.7 V and 105 °C simultaneously?
Yes. The datasheet explicitly specifies operation at VCC = 1.7 V minimum across the full −40 °C to +105 °C range, with verified write endurance of 900 k cycles and data retention exceeding 50 years at 105 °C. This dual-spec compliance is validated per AEC-Q100 Grade 2 stress testing, including high-temperature operating life (HTOL) and temperature cycling.
What SPI modes does the M95040-DRDW8TP/K support, and how are they selected?
The device supports exactly two SPI modes: CPOL=0/CPHA=0 and CPOL=1/CPHA=1. Mode selection is determined solely by the host controller's SPI peripheral configuration - no device-side registers or pins control this. In both modes, data is latched on the rising edge of C and output on the falling edge; the difference lies only in idle clock polarity (C=0 vs. C=1 when inactive), ensuring compatibility with common MCU SPI peripherals without firmware modification.
M95040-DRDW8TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95040-DRDW8TP/K FAQ
1.How can I place an order for M95040-DRDW8TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95040-DRDW8TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95040-DRDW8TP/K reliable?
The price and inventory of M95040-DRDW8TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95040-DRDW8TP/K is usually 5 days.
3.What payment methods are accepted for M95040-DRDW8TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95040-DRDW8TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95040-DRDW8TP/K?
M95040-DRDW8TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95040-DRDW8TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95040-DRDW8TP/K?
For technical support, including M95040-DRDW8TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95040-DRDW8TP/K requirements.
6.How does Aetrix verify that M95040-DRDW8TP/K is sourced from the original manufacturer or authorized distributors?
All M95040-DRDW8TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95040-DRDW8TP/K meets industry standards.
7.What is the process for return or replacement of M95040-DRDW8TP/K?
All M95040-DRDW8TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95040-DRDW8TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95040-DRDW8TP/K part is unused and in its original packaging.
Return procedure for M95040-DRDW8TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95040-DRDW8TP/K Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
