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STMicroelectronics M95040-RMN6TP
- Part No.:
- M95040-RMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95040-RMN6TP.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:9,318
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Product details
Overview
M95040-RMN6TP from STMicroelectronics is a 4-Kbit (512-byte) serial SPI bus EEPROM with 16-byte page architecture, 1.8 V to 5.5 V single-supply operation, and integrated identification page for secure parameter storage. It delivers byte/page write times ≤5 ms, >4 million write cycles, and 200-year data retention - deployed in industrial control modules for firmware configuration storage and calibration data logging.
For engineers reviewing the M95040-RMN6TP datasheet, M95040-RMN6TP pinout, M95040-RMN6TP application, or M95040-RMN6TP equivalent, key selection criteria include its 20 MHz SPI clock support, hardware/software write protection (quarter/half/whole array), ECC-protected read reliability, and ECOPACK2-compliant TSSOP8 package for space-constrained PCB layouts.
Technical Context
This device implements a standard SPI interface with CPOL=0/CPHA=0 or CPOL=1/CPHA=1 mode compatibility, using dedicated D (input), Q (output), C (clock), S (chip select), W (write protect), and HOLD (communication pause) signals. Its internal architecture includes an ECC x1 logic block per memory byte and a non-volatile status register with BP1/BP0 bits controlling software-based block protection.
The M95040-RMN6TP integrates a power-on-reset (POR) circuit that enforces instruction readiness only after VCC exceeds VRES, and supports hold-mode suspension without resetting the clock sequence - critical for multi-master SPI bus arbitration and deterministic timing in real-time embedded systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8-bit array), enabling storage of boot configuration, sensor calibration tables, or device ID data in compact MCU systems. |
| Page size | 16 bytes - defines minimum write granularity and influences firmware update efficiency and wear-leveling strategy. |
| Write time | ≤5 ms per byte or page - ensures fast field-upgradable parameter updates without blocking host CPU for extended periods. |
| Supply voltage | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers without level-shifting circuitry. |
| Operating temp | −40 °C to +85 °C - qualified for industrial automation, smart metering, and automotive body electronics environments. |
| Clock frequency | Up to 20 MHz - enables high-throughput configuration reads during system initialization or diagnostics. |
| Data retention | 200 years - guarantees long-term integrity of stored calibration coefficients or security keys across product lifecycle. |
| Write endurance | 4 million cycles - accommodates frequent runtime parameter logging (e.g., energy counters, fault history) in IoT edge nodes. |
Pinout & Package
Package: TSSOP8 (169 mil width), RoHS-compliant and halogen-free (ECOPACK2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 – VSS | Ground reference | Common return path for all I/O and supply currents; must be low-impedance to minimize noise coupling into SPI signals. |
| 2 – S | Chip select input | Active-low enable signal; falling edge initiates instruction decoding and places device in active power mode. |
| 3 – C | Serial clock input | Timing reference for all SPI transfers; latches D on rising edge and drives Q on falling edge. |
| 4 – HOLD | Hold control input | Pauses ongoing SPI communication without deselecting device; requires C to be low for valid activation/deactivation. |
| 5 – Q | Serial data output | Tri-state output delivering MSB-first read data; high-impedance when S is high or HOLD is asserted. |
| 6 – W | Hardware write protect | Low-active signal disabling all write operations regardless of WEL or BP bits - used for factory lock-down. |
| 7 – VCC | Power supply | Single 1.8–5.5 V rail powering core logic, EEPROM array, and I/O buffers; requires local 10–100 nF decoupling. |
| 8 – D | Serial data input | MSB-first input for instructions, addresses, and write data; sampled on rising edge of C. |
Key Features
| Feature | Design Value |
|---|---|
| Identification page | 16-byte dedicated area supporting permanent read-only lock (LID command) for storing cryptographic keys or device-specific identifiers. |
| ECC x1 correction | Per-byte single-bit error detection and correction improves read reliability in electrically noisy industrial environments without software overhead. |
| Flexible write protection | Software-configurable BP1/BP0 bits enable quarter/half/whole array lock, complemented by hardware W pin for irreversible protection. |
| Hold function | Enables SPI bus sharing with multiple masters by pausing transactions mid-sequence without losing state or requiring re-synchronization. |
| Power-on reset | Internal POR prevents spurious writes during power ramp-up and ensures WEL and WIP bits initialize to safe default states. |
Applications
| Industrial PLC Configuration Storage | Smart Meter Calibration Data Logging |
|---|---|
|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and firmware version flags in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Non-volatile configuration register accessed via SPI during boot and runtime reconfiguration; supports <5 ms parameter updates without interrupting control loop execution. Use Value: Enables field-upgradable machine logic without hardware revision, leveraging 200-year retention and −40 °C to +85 °C operation. |
Use Scenario: Recording energy consumption deltas, tamper-event timestamps, and metrology calibration offsets in ANSI C12.22-compliant utility meters. IC Role / Device Role / Timing Role: Secure parameter vault with ECC-protected reads and LID-locked identification page for anti-cloning compliance. Use Value: Meets IEC 62056-21 data integrity requirements via 4M-cycle endurance and hardware write protection against unauthorized firmware modification. |
| Automotive Body Control Module (BCM) | Medical Infusion Pump Settings Backup |
|
Use Scenario: Retaining seat/mirror position presets, lighting profiles, and CAN node configuration in 12 V automotive systems with wide-input DC-DC regulation. IC Role / Device Role / Timing Role: Low-voltage SPI EEPROM interfacing directly with 3.3 V microcontroller; operates down to 1.8 V during cold-crank conditions. Use Value: Eliminates external level shifters and supports AEC-Q100-relevant reliability with enhanced ESD protection and 85 °C ambient rating. |
Use Scenario: Preserving drug library definitions, dose limits, and user access credentials in battery-powered infusion pumps requiring FDA 21 CFR Part 11 audit trails. IC Role / Device Role / Timing Role: Tamper-evident configuration store with write-lockable identification page for regulatory traceability and secure boot validation. Use Value: Provides 200-year data retention for lifetime device records and ECC-protected reads to prevent dosage calculation errors from bit corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit density, quad-SPI interface, no HOLD pin, 2.7–3.6 V only | Lacks hardware HOLD and wide-voltage support; suited for high-density boot code storage, not low-voltage parameter logging | Select only if quad-SPI bandwidth >20 MHz is required and supply is strictly 3.3 V. |
| BR24G04FJ-WE2 | I²C interface (not SPI), 4 Kbit, 1.7–5.5 V, no identification page or ECC | Requires I²C master; lacks SPI timing determinism and ECC-protected reads for safety-critical data | Choose only for legacy I²C designs where pin count constraints preclude adding SPI peripherals. |
Compared with AT25DF041A-SSH-T and BR24G04FJ-WE2, the M95040-RMN6TP uniquely combines SPI-20 MHz speed, 1.8 V operation, HOLD functionality, ECC, and a lockable identification page - making it optimal for real-time, low-power, and security-sensitive embedded parameter storage.
Availability
M95040-RMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, smart meters, automotive BCMs, and medical infusion pumps requiring stable component supply across extended product lifecycles.
Supply support for M95040-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M95040-RMN6TP belongs to ST's serial EEPROM product line engineered for robust, low-power, and secure non-volatile data storage in resource-constrained embedded systems with stringent reliability requirements.
FAQ
What is the function of the HOLD pin on M95040-RMN6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low while C is low, it places Q in high-impedance and ignores D and C transitions. This enables deterministic bus arbitration in multi-master systems and allows host processors to service higher-priority interrupts mid-transfer without data loss or re-synchronization overhead.
How does the identification page differ from main memory?
The identification page is a dedicated 16-byte area accessible only via RDID/WRID commands and lockable permanently to read-only via LID. Unlike main memory, it cannot be erased by bulk erase and retains factory-programmed or user-defined security tokens, device IDs, or calibration signatures even after full memory rewrites - providing hardware-enforced separation for sensitive data.
Can M95040-RMN6TP operate reliably at 1.8 V during power-up sequences?
Yes - its 1.8 V minimum VCC rating is validated across the full −40 °C to +85 °C range. Internal POR ensures no instruction acceptance until VCC exceeds VRES (~1.5 V), and the WEL bit resets automatically at power-up. Decoupling with a 10–100 nF capacitor near VCC/VSS pins is required to maintain stability during transient load switching in low-voltage systems.
What write protection mechanisms does M95040-RMN6TP support?
It provides three layered protections: (1) hardware W pin - low-active disable of all writes; (2) software BP1/BP0 bits - configurable quarter/half/whole array lock via WRSR; and (3) identification page lock - irreversible read-only mode via LID command. These operate independently, allowing simultaneous use - e.g., W pin for factory lockdown while BP bits manage field-upgradable sections.
M95040-RMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95040-RMN6TP FAQ
1.How can I place an order for M95040-RMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95040-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95040-RMN6TP reliable?
The price and inventory of M95040-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95040-RMN6TP is usually 5 days.
3.What payment methods are accepted for M95040-RMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95040-RMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95040-RMN6TP?
M95040-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95040-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95040-RMN6TP?
For technical support, including M95040-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95040-RMN6TP requirements.
6.How does Aetrix verify that M95040-RMN6TP is sourced from the original manufacturer or authorized distributors?
All M95040-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95040-RMN6TP meets industry standards.
7.What is the process for return or replacement of M95040-RMN6TP?
All M95040-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95040-RMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95040-RMN6TP part is unused and in its original packaging.
Return procedure for M95040-RMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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