STMicroelectronics M95040-WDW6TP
- Part No.:
- M95040-WDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95040-WDW6TP.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,725
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Product details
Overview
M95040-WDW6TP from STMicroelectronics is a 4-Kbit (512-byte) serial SPI bus EEPROM with 16-byte page architecture, 20 MHz max clock frequency, and 2.5 V to 5.5 V single-supply operation. It features hardware write protection (quarter/half/whole array), identification page locking, ECC x1 error correction, and operates across -40 °C to +85 °C - deployed in industrial control modules for parameter storage and firmware revision tracking.
For engineers reviewing the M95040-WDW6TP datasheet, M95040-WDW6TP pinout, M95040-WDW6TP application, or M95040-WDW6TP equivalent, key selection criteria include supply voltage range compatibility (2.5–5.5 V), SPI mode support (CPOL=0/1, CPHA=0/1), write cycle timing (≤5 ms), identification page lockability, and ECOPACK2-compliant SO8N packaging.
Technical Context
The M95040-WDW6TP implements a standard SPI interface with CPOL/CPHA-agnostic timing: data latched on rising C edge (D input), output shifted on falling C edge (Q output). Its internal architecture includes an ECC x1 logic block per byte, transparently correcting single-bit read errors without software intervention.
It supports three protection modes via non-volatile BP1/BP0 bits in the status register - enabling quarter-array (180h–1FFh), half-array (100h–1FFh), or full-array write lock - and integrates a dedicated 16-byte identification page that can be permanently locked in read-only mode after programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8-bit array), directly addressable via 9-bit addressing (A8–A0) |
| Page size | 16 bytes - limits WRITE instruction payload and enforces page-aligned programming |
| Write time | ≤5 ms per byte or per page - enables deterministic firmware update latency in real-time systems |
| Supply voltage | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V microcontroller I/O domains without level shifting |
| Data retention | 200 years at 85 °C - validated for long-lifecycle industrial deployments without refresh |
| Endurance | 4 million write cycles - supports frequent calibration or logging operations in fielded equipment |
| ESD protection | Enhanced HBM ESD rating - improves robustness in handling and board assembly environments |
Pinout & Package
Supplied in RoHS- and halogen-free SO8N (ECOPACK2, 150 mil width) package with standard 8-pin DIP footprint and gull-wing leads.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction execution |
| C | Serial clock | Timing reference; rising edge latches D input, falling edge outputs Q data |
| D | Serial data input | MSB-first input path for instructions, addresses, and write data |
| Q | Serial data output | MSB-first output path for READ and RDSR responses; high-impedance when deselected or in HOLD |
| W | Hardware write protect | Level-sensitive input; low = disable all writes regardless of WEL or BP bits |
| HOLD | Communication pause | Active-low; suspends ongoing SPI transaction without resetting internal state or clock sequence |
| VCC | Power supply | 2.5–5.5 V nominal; requires local 10–100 nF decoupling capacitor near pins |
| VSS | Ground reference | Common return for all signals and VCC; must be low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| ECC x1 per memory byte | Corrects single-bit errors during read operations - eliminates need for external checksum validation in safety-critical parameter storage |
| Identification page (16 B) | Dedicated lockable area for device-specific calibration data or security keys - irreversible read-only lock via LID instruction |
| Flexible write protection | Software-configurable BP1/BP0 bits allow dynamic partitioning of protected zones - supports multi-tier firmware update schemes |
| Hold function | Pauses SPI communication mid-transaction without chip deselect - preserves state for MCU context switching or interrupt servicing |
| Power-on reset (POR) | Ensures WEL=0 and WIP=0 at startup - prevents spurious writes during brown-out or uncontrolled power ramp |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing temperature-compensation coefficients and sensor offset values in factory-calibrated pressure transmitters. IC Role / Device Role / Timing Role: Non-volatile parameter storage with ECC-protected reads and hardware write lock during field operation. Use Value: Ensures calibration integrity over 200-year retention and 4M-cycle endurance despite repeated recalibration events. |
Use Scenario: Holding user-selectable therapy parameters and device serialization data in portable infusion pumps. IC Role / Device Role / Timing Role: Secure configuration store with identification page lock for regulatory traceability and anti-tampering. Use Value: Prevents unauthorized modification of dose settings via permanent ID-page lockdown after final QA verification. |
| Automotive Body Control Module | Smart Energy Meter Firmware |
|
Use Scenario: Retaining seat/mirror position presets and lighting profiles across ignition cycles in 12 V vehicle systems. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 3.3 V MCU SPI peripheral with no level translation. Use Value: Operates reliably at 2.5 V minimum supply - maintains functionality during cold-crank battery dips below 9 V. |
Use Scenario: Storing tariff tables, metering logs, and firmware patch metadata in ANSI C12.22-compliant utility meters. IC Role / Device Role / Timing Role: High-endurance data logger with page-write optimization and status-register polling for write completion. Use Value: Achieves ≤5 ms write latency per 16-byte page - enables synchronized timestamped logging without MCU blocking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit density, quad-SPI capable, 1.7–3.6 V supply, no identification page | Higher density for firmware storage; lacks dedicated lockable ID page and ECC | Select when needing >4 Kbit capacity or quad-I/O speed; avoid if ID-page security or ECC is required |
| M95040-DWDW6TP | Same 4 Kbit array but 1.7–5.5 V supply range and DF suffix - adds identification page | Broader voltage range enables 1.8 V MCU compatibility; identical pinout and instruction set | Prefer for ultra-low-voltage designs; otherwise functionally interchangeable with W-suffix in 2.5–5.5 V systems |
Compared with AT25DF041A-SSH-T and M950040-DWDW6TP, the M95040-WDW6TP uniquely balances industrial-grade voltage margin (2.5–5.5 V), built-in ECC, and hardware-lockable ID page - making it optimal for parameter-critical, medium-density EEPROM use where reliability trumps raw capacity or ultra-low-voltage operation.
Availability
M95040-WDW6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and ECOPACK2-compliant packaging.
Supply support for M95040-WDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M950x0 series targets cost-sensitive, high-reliability embedded systems requiring robust serial EEPROM with enhanced data integrity - emphasizing ECC, flexible protection, and extended temperature operation.
FAQ
Does M95040-WDW6TP support both SPI Mode 0 and Mode 3?
Yes, it supports CPOL=0/CPHA=0 (Mode 0) and CPOL=1/CPHA=1 (Mode 3). Input data is latched on the rising edge of C, and output data is valid on the falling edge - matching both modes' timing requirements without configuration changes.
Can the identification page be written after power-up without additional hardware setup?
Yes - the identification page (RDID/WRID instructions) is accessible immediately after power-up once VCC stabilizes and a falling edge is applied to S. No special initialization beyond standard WREN/WRSR sequence is required.
What happens if the HOLD pin is asserted during a write cycle?
HOLD pauses communication but does not interrupt the internal write cycle (tW). The WIP bit remains set, and the device resumes normal operation upon HOLD deassertion - ensuring write completion proceeds autonomously without MCU supervision.
Is the SO8N package of M95040-WDW6TP compatible with standard 150-mil SOIC footprints?
Yes - the SO8N (ECOPACK2) package has 150 mil width, 1.27 mm pitch, and gull-wing leads conforming to JEDEC MS-012, making it mechanically and solder-reflow compatible with legacy SOIC-8 footprints without layout modification.
M95040-WDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95040-WDW6TP FAQ
1.How can I place an order for M95040-WDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95040-WDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95040-WDW6TP reliable?
The price and inventory of M95040-WDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95040-WDW6TP is usually 5 days.
3.What payment methods are accepted for M95040-WDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95040-WDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95040-WDW6TP?
M95040-WDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95040-WDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95040-WDW6TP?
For technical support, including M95040-WDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95040-WDW6TP requirements.
6.How does Aetrix verify that M95040-WDW6TP is sourced from the original manufacturer or authorized distributors?
All M95040-WDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95040-WDW6TP meets industry standards.
7.What is the process for return or replacement of M95040-WDW6TP?
All M95040-WDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95040-WDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95040-WDW6TP part is unused and in its original packaging.
Return procedure for M95040-WDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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