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STMicroelectronics M95040-WMN6P
- Part No.:
- M95040-WMN6P
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95040-WMN6P.pdf
- Description:
- IC EEPROM 4KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:20,238
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Product details
Overview
M95040-WMN6P from STMicroelectronics is a 4-Kbit (512-byte) serial SPI bus EEPROM organized as 512 × 8 bits, operating from 2.5 V to 5.5 V supply, supporting up to 20 MHz clock frequency, with 16-byte page write capability and hardware/software write protection. It is used in industrial control modules for storing calibration data, device configuration, and firmware patch metadata.
For engineers reviewing the M95040-WMN6P datasheet, M95040-WMN6P pinout, M95040-WMN6P application, or M95040-WMN6P equivalent, key selection criteria include its 4-Million write cycle endurance, 200-year data retention, ECOPACK2-compliant SO8N package, and support for SPI modes CPOL=0/CPHA=0 and CPOL=1/CPHA=1 with HOLD and W pin-based protection.
Technical Context
This EEPROM implements a full SPI interface with dedicated HOLD and WRITE PROTECT inputs, enabling pause-on-demand communication and hardware-level memory locking independent of status register settings. Its internal ECC x1 logic corrects single-bit errors per byte during read operations, improving reliability without protocol overhead.
The device features non-volatile BP0/BP1 bits controlling quarter/half/whole array write protection, plus an optional identification page (available only on DF variants - not applicable to M95040-WMN6P), and integrates a power-on reset (POR) circuit ensuring safe initialization before instruction acceptance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8 bits) - fixed capacity for compact configuration storage without external address decoding |
| Interface | SPI bus (CPOL=0/CPHA=0 or CPOL=1/CPHA=1) - compatible with standard MCU SPI peripherals without custom timing logic |
| Write speed | Page Write ≤ 5 ms - enables fast field-updatable parameter writes across 16-byte boundaries |
| Supply voltage | 2.5 V to 5.5 V - supports direct interfacing with 3.3 V and 5 V logic systems without level shifters |
| Data retention | >200 years at +25 °C - ensures long-term validity of stored calibration or security keys in unpowered systems |
| Endurance | >4 million write cycles - suitable for high-frequency logging or dynamic configuration updates in industrial controllers |
| Operating temp | −40 °C to +85 °C - qualified for use in extended-temperature industrial and automotive under-hood environments |
Pinout & Package
Supplied in RoHS- and halogen-free SO8N (ECOPACK2) package, 150 mil width, with standard 8-pin DIP footprint and pin 1 indicator notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip Select | Active-low enable signal; falling edge required after power-up to initiate first instruction; deselects device and places Q in high-impedance state |
| C | Serial Clock | Input timing reference; latches D on rising edge, drives Q on falling edge; supports up to 20 MHz operation |
| D | Serial Data Input | MSB-first input for instructions, addresses, and write data; sampled on rising edge of C |
| Q | Serial Data Output | MSB-first output for READ and RDSR responses; high-impedance when S is high or HOLD is active |
| W | Write Protect | Hardware-level lock: driven low to disable all write operations regardless of WEL or BP bits; must not float |
| HOLD | Communication Hold | Pauses ongoing SPI transfer without resetting internal state; requires S low and C low for valid assertion/deassertion |
| VCC | Supply Voltage | 2.5–5.5 V power rail; requires local 10–100 nF decoupling capacitor near pins |
| VSS | Ground | Reference for all I/O and internal circuitry; must be connected directly to system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| ECC x1 error correction | Single-bit error detection and correction per byte during read - eliminates need for external CRC validation in safety-critical storage |
| Hardware write protect (W pin) | Physical disable of all write functions independent of software status register - prevents accidental overwrites during power transients |
| HOLD functionality | Non-disruptive pause of SPI transfers while maintaining internal address and instruction state - enables time-slicing with shared bus masters |
| Block protection via BP0/BP1 | Configurable quarter/half/full memory array lock using non-volatile status register bits - supports hierarchical firmware partitioning |
| Power-on reset (POR) | Internal POR circuit holds device inactive until VCC stabilizes within spec - prevents spurious writes during brown-out conditions |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) |
|---|---|
Use Scenario: Storing runtime-calibrated sensor offsets and actuator trim values in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Non-volatile configuration register holding persistent operational parameters updated infrequently but requiring guaranteed integrity across power cycles. Use Value: 4-million-cycle endurance allows daily recalibration logging over 10+ years; 200-year retention ensures firmware compatibility across product lifecycle extensions. | Use Scenario: Holding vehicle-specific door lock timing profiles, mirror position presets, and lighting fade curves in BCM microcontrollers. IC Role / Device Role / Timing Role: Dedicated SPI EEPROM co-located with MCU for secure, low-power parameter storage independent of main flash memory wear. Use Value: Hardware W pin prevents corruption during battery voltage sag; −40 °C to +85 °C rating matches under-dash thermal requirements. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Patch Log |
Use Scenario: Archiving pump motor calibration coefficients, flow sensor linearization tables, and safety-critical dose limits in Class II medical devices. IC Role / Device Role / Timing Role: Tamper-resistant parameter vault with ECC-enabled reads to ensure delivery accuracy compliance per IEC 62304. Use Value: ECC x1 eliminates soft-error-induced dose miscalculation; write-protection hierarchy prevents unauthorized parameter modification. | Use Scenario: Recording firmware update timestamps, patch version hashes, and rollback counters in utility-grade electricity meters with 15+ year field life. IC Role / Device Role / Timing Role: Field-upgradable configuration log with atomic page writes and block-locking to preserve critical metering constants. Use Value: 5 ms page write enables rapid patch commit; BP0/BP1 bits lock base calibration constants while allowing dynamic parameter updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit density (512 KB), quad-SPI capable, 3.0–3.6 V only, no HOLD pin | Targeted at high-density code shadowing; lacks HOLD and wide-VCC flexibility | Select only if >4 Kbit capacity and quad-I/O bandwidth are required; not drop-in for M95040-WMN6P footprint or voltage range |
| BR24G04FJ-WE2 | I²C interface (not SPI), 4 Kbit, 1.7–5.5 V, no hardware W pin, no HOLD | Designed for space-constrained I²C systems; lacks SPI timing control and dual protection layers | Choose only when I²C bus topology is fixed and HOLD/W pin functionality is unnecessary |
Compared with AT25DF041A-SSH-T and BR24G04FJ-WE2, M95040-WMN6P uniquely combines SPI compatibility, hardware W/HOLD pins, 2.5–5.5 V operation, and ECC - making it optimal for robust, low-pin-count industrial parameter storage where deterministic timing and fault resilience are mandatory.
Availability
M95040-WMN6P is available at Aetrix Electronics and suitable for industrial PLCs, automotive body control modules, medical infusion pumps, and smart energy meters requiring stable component supply across multi-year production programs.
Supply support for M95040-WMN6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
M95040-WMN6P belongs to ST's serial EEPROM product line, engineered specifically for reliable, low-power, SPI-based configuration and calibration data storage in harsh-environment embedded systems.
FAQ
What SPI modes does M95040-WMN6P support?
M95040-WMN6P supports two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C and output on the falling edge. The difference lies only in idle clock polarity - C remains low in mode (0,0) and high in mode (1,1). No mode configuration is required on the device side; compatibility is ensured by MCU peripheral setup.
How does the HOLD function interact with chip select (S)?
HOLD can only be asserted when S is low (device selected); asserting HOLD while S is high has no effect. During HOLD, Q goes high-impedance and D/C are ignored, but internal address and instruction state are preserved. To resume, drive HOLD high while C is low - then continue clocking. Deselecting S during HOLD resets the device state, which is a valid recovery method if synchronization is lost.
Can the write protect (W) pin override software-based block protection?
Yes - the W pin provides unconditional hardware-level write disable. When W is driven low, all write operations (WRITE, WRSR, etc.) are blocked regardless of WEL bit state or BP0/BP1 configuration. This is a fail-safe mechanism: even if firmware erroneously enables writes or corrupts the status register, physical grounding of W prevents memory modification. W must be actively driven - never left floating.
Is the identification page available on M95040-WMN6P?
No - the identification page (16 bytes, lockable via LID instruction) is exclusive to the M95040-DF variant. M95040-WMN6P is part of the M950x0-W family and contains only the standard 512-byte memory array with no additional ID page. Its ordering code suffix "W" confirms wide-voltage (2.5–5.5 V) operation and standard feature set, excluding DF-specific enhancements.
M95040-WMN6P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95040-WMN6P FAQ
1.How can I place an order for M95040-WMN6P through Aetrix?
Please submit a Request for Quotation (RFQ) for M95040-WMN6P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95040-WMN6P reliable?
The price and inventory of M95040-WMN6P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95040-WMN6P is usually 5 days.
3.What payment methods are accepted for M95040-WMN6P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95040-WMN6P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95040-WMN6P?
M95040-WMN6P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95040-WMN6P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95040-WMN6P?
For technical support, including M95040-WMN6P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95040-WMN6P requirements.
6.How does Aetrix verify that M95040-WMN6P is sourced from the original manufacturer or authorized distributors?
All M95040-WMN6P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95040-WMN6P meets industry standards.
7.What is the process for return or replacement of M95040-WMN6P?
All M95040-WMN6P units undergo pre-shipment inspection (PSI). If there is an issue with M95040-WMN6P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95040-WMN6P part is unused and in its original packaging.
Return procedure for M95040-WMN6P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95040-WMN6P Tags
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