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Home > Products > Integrated Circuits (ICs) > Memory > Memory

STMicroelectronics M95080-DRMN3TP/K

Name: M95080-DRMN3TP/K
Brand: STMicroelectronics
SKU: M95080-DRMN3TP/K
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: M95080-DRMN3TP/K

Manufacturer:: STMicroelectronics

Category:: Memory

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: M95080-DRMN3TP/K.pdf

Description:: IC EEPROM 8KBIT SPI 20MHZ 8SOIC

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Product details

Overview

M95080-DRMN3TP/K from STMicroelectronics is an automotive-grade 8-Kbit serial SPI EEPROM with AEC-Q100 Grade 0 qualification, operating up to 145 °C at V_CC = 2.5–5.5 V. It features 1024 × 8-bit memory organized in 32 pages of 32 bytes, embedded ECC logic for data integrity, and a dedicated 32-byte lockable Identification Page for device ID or secure parameter storage.

For engineers reviewing the M95080-DRMN3TP/K datasheet, M95080-DRMN3TP/K pinout, M95080-DRMN3TP/K application, or M95080-DRMN3TP/K equivalent, key selection criteria include high-temperature endurance (600 k write cycles at 125 °C), configurable block write protection (1/4, 1/2, or full memory), and 20 MHz max clock speed at V_CC ≥ 4.5 V.

Technical Context

This SPI EEPROM implements CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes with rising-edge input sampling and falling-edge output shifting. Its protocol control includes edge- and level-sensitive Chip Select (S) with automatic WEL latching on WREN and auto-clear on WRDI or write completion.

The Status Register (b7–b0) provides real-time WIP and WEL flags plus non-volatile BP1/BP0 block protection bits and SRWD bit that couples with the physical W pin to freeze status register writes when W is low and SRWD=1 - enabling hardware-enforced write lock.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	8 Kbit (1024 × 8 bits), organized as 32 pages × 32 bytes - enables efficient firmware patching and parameter logging with page-level atomic writes.
Max clock frequency	20 MHz at V_CC ≥ 4.5 V - supports high-throughput configuration loading in engine control units without bus bottlenecks.
Write endurance	600 k cycles at 125 °C - ensures reliable calibration storage over full automotive lifetime under hood-high-temperature conditions.
Data retention	50 years at 125 °C - guarantees persistent storage of safety-critical vehicle configuration data across extended service intervals.
Operating temperature	−40 °C to +145 °C - qualified per AEC-Q100 Grade 0 for placement in powertrain, transmission, and under-hood modules.
Write protection	Configurable via BP1/BP0 bits: 1/4, 1/2, or full memory block lock - prevents accidental overwrite of boot code or regulatory compliance parameters.
ESD rating	4000 V HBM - withstands assembly handling and in-vehicle electrostatic events without latch-up or data corruption.

Pinout & Package

Package: SO8 (MN), 150 mil width, RoHS-compliant and halogen-free ECOPACK2®.

Pin/Terminal	Circuit Role	Design Meaning
S	Chip Select	Edge- and level-sensitive enable: requires falling edge + sustained low to initiate command decoding; deselecting resets internal state.
C	Serial Clock	Input synchronizing all SPI transfers; rising edge latches D, falling edge shifts Q - supports both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes.
D	Serial Data Input	Receives instruction opcodes, address bytes, and write data MSB-first on rising C edge; ignored during Hold mode.
Q	Serial Data Output	Drives read data MSB-first on falling C edge; enters high-Z when S is high or HOLD is asserted.
HOLD	Communication Pause	Halts ongoing SPI transfer without deselecting device; resumes from same bit position when deasserted with C low.
W	Write Protect Control	Hardware gate for Status Register writes: when low and SRWD=1, blocks WRSR - enforces irreversible lock of BP1/BP0 settings.
V_SS	Ground Reference	Common return for all I/O and V_CC; must be low-impedance connection to avoid noise-induced command errors.
V_CC	Supply Voltage	1.7–5.5 V operation; 2.5–5.5 V required for 145 °C grade - enables direct interface with 3.3 V or 5 V microcontroller buses.

Key Features

Feature	Design Value
Embedded ECC logic	Single-bit error correction per 32-byte page - maintains data integrity in electrically noisy automotive environments without host-side software overhead.
Identification Page	32-byte dedicated area readable via RDID, writable via WRID, lockable via LID - stores immutable device ID or encrypted calibration keys.
Short write cycle time	≤4 ms for byte or page write - minimizes bus occupation time during critical runtime updates (e.g., adaptive learning values).
Schmitt trigger inputs	On S, C, D, HOLD, W - rejects <10 ns glitches and ensures robust operation in high-EMI powertrain subsystems.
Hold mode	Pauses active SPI transaction mid-byte without losing synchronization - allows microcontroller to service higher-priority interrupts then resume transparently.

Applications

Engine Control Unit (ECU)

Advanced Driver Assistance Systems (ADAS)

Use Scenario: Storing adaptive fuel trim tables and misfire counters updated during vehicle operation.

IC Role / Device Role / Timing Role: Nonvolatile configuration memory with guaranteed 50-year retention at 125 °C and 600 k write cycles under thermal stress.

Use Value: Eliminates need for external backup capacitors or wear-leveling firmware, reducing BOM cost and validation effort.

Use Scenario: Holding camera calibration offsets and radar sensor fusion coefficients requiring field updates.

IC Role / Device Role / Timing Role: Secure parameter store with lockable Identification Page - prevents unauthorized modification of safety-critical tuning data.

Use Value: Enables OTA update of calibration data while maintaining cryptographic binding to hardware identity stored in RDID-accessible page.

Transmission Control Module (TCM)

Body Control Module (BCM)

Use Scenario: Logging gear shift history and clutch wear metrics for predictive maintenance diagnostics.

IC Role / Device Role / Timing Role: High-endurance data logger supporting 4 million writes at 25 °C and 600 k at 125 °C - matches TCM thermal profile.

Use Value: Supports 15+ year vehicle lifespan with daily diagnostic writes without requiring host wear-leveling algorithms.

Use Scenario: Storing user preferences (seat position, mirror angle, lighting profiles) persisting across ignition cycles.

IC Role / Device Role / Timing Role: Low-power SPI EEPROM with standby current <5 μA - extends battery life in always-on BCM sleep states.

Use Value: Reduces quiescent current burden versus flash-based alternatives, meeting ISO 19453-3 leakage requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT25DF041A-SSH-T	4-Mbit density, quad SPI interface, no built-in ECC, max 85 °C industrial grade	Lacks AEC-Q100 qualification and high-temp endurance; suitable only for cabin electronics	Select only if higher density and quad I/O bandwidth outweigh need for automotive reliability and 145 °C operation.
BR24G08FJ-3GE2	I²C interface (not SPI), 8-Kbit, 105 °C max, no Identification Page or SRWD/W pin coupling	No hardware-enforced status register lock; incompatible with existing SPI bus topology	Choose only for space-constrained I²C designs where pin count reduction justifies loss of AEC-Q100 Grade 0 and programmable block protection.

Compared with AT25DF041A-SSH-T and BR24G08FJ-3GE2, M95080-DRMN3TP/K uniquely delivers AEC-Q100 Grade 0 qualification, 145 °C operation with validated 600 k write cycles, and hardware-gated status register locking - making it the sole choice for safety-critical powertrain and ADAS parameter storage.

Availability

M95080-DRMN3TP/K is available at Aetrix Electronics and suitable for engine control units, ADAS sensors, transmission control modules, and body control modules requiring stable component supply across extended automotive lifecycles.

Supply support for M95080-DRMN3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

M95080-DRMN3TP/K belongs to ST's automotive EEPROM product line, engineered specifically for mission-critical data storage in harsh-temperature environments where AEC-Q100 Grade 0 reliability and hardware-enforced write protection are mandatory.

FAQ

What is the maximum clock frequency supported by M95080-DRMN3TP/K at 3.3 V supply?

At V_CC = 3.3 V, the device supports up to 10 MHz clock frequency, as specified in the datasheet's AC characteristics table for voltage range R (2.5–5.5 V). This ensures compatibility with standard 3.3 V microcontroller SPI peripherals without timing margin violations.

How does the Identification Page differ from main memory in terms of access and protection?

The Identification Page is a separate 32-byte area accessible only via RDID/WRID instructions - not through standard READ/WRITE commands. It can be permanently locked to read-only using the LID instruction, and its contents (including ST device ID) are retained independently of main memory erase cycles.

Can the Block Protect bits (BP1/BP0) be modified after the SRWD bit is set to 1 and the W pin is pulled low?

No - once SRWD = 1 and W is driven low, the Status Register becomes write-protected; BP1/BP0 bits cannot be altered until W is returned high. This hardware-enforced freeze prevents accidental or malicious reconfiguration of memory protection boundaries in deployed systems.

Is M95080-DRMN3TP/K compatible with standard SPI controllers without custom driver development?

Yes - it supports standard SPI modes CPOL=0/CPHA=0 and CPOL=1/CPHA=1 with conventional MOSI/MISO/SCLK/SS signaling. No special timing or protocol extensions are required; existing SPI drivers can interface directly using WREN, WRITE, READ, and RDSR instructions defined in the datasheet.

M95080-DRMN3TP/K Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 8Kbit

Memory Organization:: 1K x 8

Memory Interface:: SPI

Clock Frequency:: 20 MHz

Write Cycle Time - Word, Page:: 4ms

Access Time:: -

Voltage - Supply:: 1.8V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: Automotive

Qualification:: AEC-Q100

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

M95080-DRMN3TP/K FAQ

1.How can I place an order for M95080-DRMN3TP/K through Aetrix?

Please submit a Request for Quotation (RFQ) for M95080-DRMN3TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M95080-DRMN3TP/K reliable?

The price and inventory of M95080-DRMN3TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95080-DRMN3TP/K is usually 5 days.

3.What payment methods are accepted for M95080-DRMN3TP/K?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95080-DRMN3TP/K transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M95080-DRMN3TP/K?

M95080-DRMN3TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M95080-DRMN3TP/K order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M95080-DRMN3TP/K?

For technical support, including M95080-DRMN3TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95080-DRMN3TP/K requirements.

6.How does Aetrix verify that M95080-DRMN3TP/K is sourced from the original manufacturer or authorized distributors?

All M95080-DRMN3TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95080-DRMN3TP/K meets industry standards.

7.What is the process for return or replacement of M95080-DRMN3TP/K?

All M95080-DRMN3TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95080-DRMN3TP/K, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M95080-DRMN3TP/K part is unused and in its original packaging.

Return procedure for M95080-DRMN3TP/K:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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