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STMicroelectronics M95080-DRMN8TP/K

Part No.:
M95080-DRMN8TP/K
Manufacturer:
STMicroelectronics
Category:
Memory
Package:
8-SOIC (0.154", 3.90mm Width)
Datasheet:
AetrixM95080-DRMN8TP/K.pdf
Description:
IC EEPROM 8KBIT SPI 20MHZ 8SO
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,098

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Product details

Overview

M95080-DRMN8TP/K from STMicroelectronics is an 8-Kbit serial SPI EEPROM with 1024 × 8-bit organization, 32-byte page size, and extended operation up to 105 °C at VCC = 1.7–5.5 V. It features embedded ECC logic for enhanced data integrity, a dedicated 32-byte lockable Identification Page, and hardware write protection via SRWD/BP bits and W pin - deployed in automotive body control modules for calibration storage and fault log retention.

For engineers reviewing the M95080-DRMN8TP/K datasheet, M95080-DRMN8TP/K pinout, M95080-DRMN8TP/K application, or M95080-DRMN8TP/K equivalent, key selection criteria include guaranteed 105 °C endurance (900k write cycles), SPI clock support up to 20 MHz at 4.5–5.5 V, Schmitt-trigger noise immunity on all inputs, and AEC-Q100 Grade 2 qualification for automotive use.

Technical Context

The device implements a true EEPROM memory array with byte-alterable capability and built-in single-bit Error Correction Code (ECC x1) logic that detects and corrects bit errors during read operations. Its SPI interface supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, with data latched on rising C edge and output shifted on falling C edge.

Write protection is enforced through dual-layer control: non-volatile Block Protect (BP1/BP0) bits define protected memory regions (none, upper quarter, upper half, or full array + ID page), while Status Register Write Disable (SRWD) combined with the W pin enables hardware-level locking of BP/SRWD configuration - preventing accidental or unauthorized status register modification.

Key Specifications

ParameterValue and Actual Design Meaning
Memory Size8 Kbit (1024 × 8 bits), organized as 32 pages of 32 bytes - enables efficient firmware parameter updates without full-erase overhead.
Operating Temperature−40 °C to +105 °C - qualified per AEC-Q100 Grade 2, suitable for under-hood automotive ECUs.
Supply Voltage1.7 V to 5.5 V - supports wide-input industrial and automotive power rails including 3.3 V and 5 V systems.
SPI Clock FrequencyUp to 20 MHz (VCC ≥ 4.5 V), 10 MHz (≥2.5 V), 5 MHz (≥1.7 V) - enables fast boot-time configuration loading in real-time systems.
Write Endurance900 k cycles at 105 °C - ensures reliable logging over 10+ years in high-temp engine control applications.
Data Retention>50 years at 105 °C - guarantees long-term calibration stability without periodic refresh.
ESD Protection4000 V HBM - provides robust handling during board assembly and field service.

Pinout & Package

Package: SO8 (MN), 150-mil width, RoHS-compliant and halogen-free ECOPACK2®.

Pin/TerminalCircuit RoleDesign Meaning
SChip SelectActive-low enable signal; falling edge initiates command decoding and must remain low throughout instruction sequence.
CSerial ClockSynchronizes data transfer; input sampled on rising edge, Q output changes after falling edge - supports standard SPI modes 0 and 3.
DSerial Data InputAccepts instructions, addresses, and write data; MSB-first, latched on rising C edge.
QSerial Data OutputProvides read data and status bits; high-impedance when S is high or HOLD is active.
WWrite ProtectHardware control for Status Register write-locking when SRWD = 1 - prevents unintended BP bit changes during system operation.
HOLDHold ControlPauses ongoing SPI transaction without deselecting device; requires C low to activate - preserves clock state during interrupt servicing.
VSSGround ReferenceCommon return path for all signals and VCC; must be low-impedance to ensure noise immunity and stable ECC operation.
VCCSupply VoltagePower input supporting 1.7–5.5 V range; internal voltage regulator enables consistent timing across voltage variations.

Key Features

FeatureDesign Value
Embedded ECC x1 LogicCorrects single-bit errors and detects double-bit errors during read operations - eliminates need for external error-handling firmware in safety-critical storage.
Lockable Identification Page32-byte dedicated area with LID instruction; once locked, contents become read-only - secures ST device ID and user-defined calibration constants against overwrite.
Multi-Level Write ProtectionCombines volatile WEL bit, non-volatile BP1/BP0 block bits, and SRWD+W pin interlock - enables hierarchical protection for factory programming, field updates, and runtime safeguarding.
Schmitt Trigger InputsApplied to S, C, D, HOLD, and W pins - rejects noise transients up to 30% VCC, ensuring reliable command recognition in electrically noisy automotive environments.
Fast Write TimingByte and Page Write both complete within 4 ms - reduces firmware update latency and improves system responsiveness during reconfiguration.

Applications

Automotive Body Control Unit (BCU)Industrial PLC Configuration Storage

Use Scenario: Storing door actuator calibration offsets, seat position profiles, and lighting dimming curves across vehicle lifetime.

IC Role / Device Role / Timing Role: Non-volatile parameter repository with AEC-Q100 Grade 2 qualification and 105 °C operation - retains settings during engine-off thermal soak and hot-cranking events.

Use Value: Eliminates battery-backed SRAM; leverages 50-year data retention at 105 °C to guarantee calibration persistence over full vehicle service life without maintenance.

Use Scenario: Holding I/O mapping tables, PID tuning parameters, and firmware update flags in modular automation controllers.

IC Role / Device Role / Timing Role: SPI-configurable persistent memory interfaced directly to ARM Cortex-M7 microcontroller - enables zero-latency access to critical runtime parameters during cold start.

Use Value: Uses 20 MHz SPI clock at 5 V to load full configuration in <10 ms, reducing system boot time by 35% compared to legacy I²C EEPROMs.

Medical Infusion Pump CalibrationSmart Energy Meter Firmware Patch Storage

Use Scenario: Securing drug delivery rate coefficients, sensor offset corrections, and usage audit logs in Class II medical devices.

IC Role / Device Role / Timing Role: Tamper-resistant storage with lockable Identification Page - stores manufacturer-calibrated values that cannot be altered post-certification.

Use Value: LID instruction permanently locks ID page after factory programming, satisfying IEC 62304 traceability requirements for immutable calibration data.

Use Scenario: Storing delta patches for firmware upgrades and tariff schedule updates in utility-grade electricity meters operating in outdoor enclosures.

IC Role / Device Role / Timing Role: High-reliability EEPROM with 900k write cycles at 105 °C - withstands repeated field updates in thermally stressed meter housings near transformers.

Use Value: Achieves >15-year field life with daily patch writes, exceeding ANSI C12.22 security and longevity mandates for AMI infrastructure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
AT25080B-SSHL-T8-Kbit SPI EEPROM, 10 MHz max clock at 2.5–5.5 V, no embedded ECC, AEC-Q100 not specified.Lacks ECC and automotive qualification - suitable for cost-sensitive industrial controls but not safety-critical automotive BCU.Select only if AEC-Q100 Grade 2 and ECC are not required; verify 105 °C endurance spec separately.
BR24G08NUX-5TR8-Kbit I²C EEPROM, 1 MHz max, 1.7–5.5 V, integrated write-cycle timer, no hold pin or identification page.I²C interface limits speed and increases MCU GPIO overhead; no HOLD or ID page functionality.Choose only for existing I²C bus designs where SPI migration is impractical; expect longer write latency and no hardware pause capability.

Compared with AT25080B-SSHL-T and BR24G08NUX-5TR, the M95080-DRMN8TP/K uniquely delivers AEC-Q100 Grade 2 compliance, embedded ECC, 20 MHz SPI performance, and a lockable Identification Page - making it the sole option for automotive and medical applications requiring certified data integrity and secure parameter storage.

Availability

M95080-DRMN8TP/K is available at Aetrix Electronics and suitable for automotive body control units, industrial PLCs, medical infusion pumps, and smart energy meters requiring stable component supply across extended temperature and long product lifecycles.

Supply support for M95080-DRMN8TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

The M95080-DRMN8TP/K belongs to ST's automotive-qualified serial EEPROM product line, engineered specifically for mission-critical non-volatile storage in harsh environments where data integrity, temperature resilience, and long-term reliability are mandatory.

FAQ

What is the function of the HOLD pin on the M95080-DRMN8TP/K?

The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting the clock sequence. When driven low while Serial Clock (C) is low, it places Q in high-impedance and ignores D and C transitions. This allows the host MCU to service interrupts or perform other tasks while preserving the exact state of the current transaction - essential for deterministic real-time systems.

How does the Identification Page differ from main memory in usage and protection?

The 32-byte Identification Page resides outside the main 1-Kbyte array and contains factory-programmed ST device ID bytes plus user-allocated space. Unlike main memory, it can be permanently locked via the LID instruction - after locking, all reads succeed but writes are blocked even if WEL=1 and W pin is high. This ensures immutable storage of calibration or security keys post-manufacturing.

Can the M95080-DRMN8TP/K operate reliably at 1.7 V and 105 °C simultaneously?

Yes - the datasheet explicitly specifies 5 MHz SPI clock support and 900k write cycles at 105 °C across the full 1.7–5.5 V VCC range. Its internal voltage regulation and process-hardened EEPROM cells maintain timing margins and endurance under simultaneous low-voltage/high-temperature stress, validated per AEC-Q100 Grade 2 test conditions.

What happens if the W pin is held low while SRWD = 1?

When SRWD = 1 and W is low, the Status Register becomes permanently write-protected: WRSR commands are discarded, and BP1/BP0 bits cannot be modified. The only recovery method is to drive W high - this immediately restores Status Register writability. This interlock prevents accidental corruption of memory protection settings during brown-out or reset sequences where W may float low.

M95080-DRMN8TP/K Specifications

Product attributes
Attribute value
Manufacturer:
STMicroelectronics
Series:
-
Package/Case:
8-SOIC (0.154", 3.90mm Width)
Packaging:
Tape & Reel (TR)
Product Status:
Active
Programmable:
Not Verified
Memory Type:
Non-Volatile
Memory Format:
EEPROM
Technology:
EEPROM
Memory Size:
8Kbit
Memory Organization:
1K x 8
Memory Interface:
SPI
Clock Frequency:
20 MHz
Write Cycle Time - Word, Page:
4ms
Access Time:
-
Voltage - Supply:
1.8V ~ 5.5V
Operating Temperature:
-40°C ~ 105°C (TA)
Grade:
Automotive
Qualification:
AEC-Q100
Mounting Type:
Surface Mount
Supplier Device Package:
8-SO

M95080-DRMN8TP/K FAQ

1.How can I place an order for M95080-DRMN8TP/K through Aetrix?

Please submit a Request for Quotation (RFQ) for M95080-DRMN8TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M95080-DRMN8TP/K reliable?

The price and inventory of M95080-DRMN8TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95080-DRMN8TP/K is usually 5 days.

3.What payment methods are accepted for M95080-DRMN8TP/K?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95080-DRMN8TP/K transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M95080-DRMN8TP/K?

M95080-DRMN8TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M95080-DRMN8TP/K order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M95080-DRMN8TP/K?

For technical support, including M95080-DRMN8TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95080-DRMN8TP/K requirements.

6.How does Aetrix verify that M95080-DRMN8TP/K is sourced from the original manufacturer or authorized distributors?

All M95080-DRMN8TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95080-DRMN8TP/K meets industry standards.

7.What is the process for return or replacement of M95080-DRMN8TP/K?

All M95080-DRMN8TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95080-DRMN8TP/K, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M95080-DRMN8TP/K part is unused and in its original packaging.

Return procedure for M95080-DRMN8TP/K:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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