STMicroelectronics M95080-RMN6TP
- Part No.:
- M95080-RMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95080-RMN6TP.pdf
- Description:
- IC EEPROM 8KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:6,930
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Product details
Overview
M95080-RMN6TP from STMicroelectronics is an 8-Kbit serial SPI bus EEPROM organized as 1024 × 8 bits, operating from 1.8 V to 5.5 V over –40 °C to +85 °C. It features 32-byte page write, 5 ms max byte/page write time, 20 MHz clock support, and includes a dedicated 32-byte identification page with permanent lock capability for secure parameter storage in industrial control modules.
For engineers reviewing the M95080-RMN6TP datasheet, M95080-RMN6TP pinout, M95080-RMN6TP application, or M95080-RMN6TP equivalent, this device serves as a low-voltage, high-reliability nonvolatile memory for firmware configuration storage, calibration data retention, and secure device identity management in space-constrained embedded systems.
Technical Context
The M95080-RMN6TP implements a full SPI interface compliant with CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, with input sampling on rising C edge and output valid on falling C edge. Its internal ECC x1 logic corrects single-bit errors per byte during read operations, enhancing data integrity without protocol overhead.
It integrates a nonvolatile status register (BP1/BP0/SRWD/WEL/WIP) enabling software- and hardware-based memory protection: BP1/BP0 configure quarter/half/whole array write lock, while SRWD + W pin combination enables hardware-locked status register mode. The HOLD pin allows communication suspension without chip deselection or state reset.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 8 Kbit (1024 × 8), sufficient for bootloader config, sensor calibration tables, and device ID storage |
| Supply voltage | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V logic and legacy 3.3/5 V microcontrollers |
| Write cycle time | ≤5 ms per byte or 32-byte page - enables fast field updates without system timeout constraints |
| Max clock frequency | 20 MHz - delivers up to 2.5 MB/s effective serial throughput for rapid bulk reads/writes |
| Data retention | 200 years at 25 °C - ensures long-term reliability in unattended infrastructure monitoring nodes |
| Endurance | 4 million write cycles - supports daily firmware patching or logging over >10-year product lifetime |
| ECC protection | Single-bit error correction per byte - eliminates need for external checksum layers in safety-critical logging |
Pinout & Package
Package: TSSOP8 (169 mil width), RoHS-compliant and halogen-free (ECOPACK2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselects Q to high-Z |
| C | Serial clock | Timing reference; rising edge latches D, falling edge outputs Q; supports 20 MHz operation |
| D | Serial data input | MSB-first input for instructions, addresses, and write data; sampled on rising C edge |
| Q | Serial data output | MSB-first output for READ/RDSR/RDID; driven on falling C edge; high-Z during HOLD/S high |
| W | Write protect | Hardware control for SRWD-based status register lock; must be stable during all writes |
| HOLD | Communication hold | Pauses ongoing SPI transfer without resetting internal state; requires S low to activate |
| VCC | Power supply | 1.8–5.5 V input; requires local 10–100 nF decoupling capacitor near pins |
| VSS | Ground | Signal and supply reference; must be connected directly to system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Identification page | 32-byte dedicated memory area with LID instruction for permanent read-only lock, ideal for storing cryptographic keys or factory calibration data |
| Flexible memory protection | Software-configurable (BP1/BP0) quarter/half/whole array lock + hardware-enforced (SRWD+W) status register freeze |
| Robust SPI timing | Supports both CPOL/CPHA = (0,0) and (1,1) modes, ensuring interoperability with diverse MCU SPI peripherals |
| Enhanced data integrity | On-the-fly ECC x1 per byte corrects single-bit read errors, eliminating silent corruption in long-term storage applications |
| Low-voltage operation | 1.8 V minimum VCC enables direct integration with ultra-low-power microcontrollers (e.g., STM32L series) without level shifters |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and firmware version flags in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed via SPI during boot and runtime reconfiguration. Use Value: Enables field-upgradable control logic without requiring external memory controllers or battery-backed SRAM. |
Use Scenario: Holding sensor offset/gain coefficients, patient-specific therapy profiles, and regulatory compliance logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant data vault with identification page lock for FDA/IEC 62304 traceability. Use Value: Meets medical-grade data integrity requirements via ECC and hardware-locked status register, reducing validation effort. |
| Automotive Body Control Module (BCM) | Smart Meter Firmware Parameter Storage |
|
Use Scenario: Saving seat/mirror position presets, lighting profiles, and CAN node configuration across ignition cycles in 12 V automotive systems. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced to 3.3 V BCM microcontroller; withstands load-dump transients via robust ESD design. Use Value: Operates reliably at 1.8 V during cold-crank conditions where supply dips below 2.5 V, unlike M95080-W variants. |
Use Scenario: Storing tariff schedules, metering constants, and firmware update signatures in utility-grade electricity meters deployed for 20+ years. IC Role / Device Role / Timing Role: Long-life nonvolatile memory with 200-year data retention and 4M-cycle endurance for daily billing log writes. Use Value: Eliminates need for periodic battery replacement or memory refresh, lowering total cost of ownership in remote deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25080B-SSHL-T | 8 Kbit SPI EEPROM, 2.5–5.5 V supply, no identification page, no ECC, 10 MHz max clock | Lacks secure ID page and ECC; suitable only for basic configuration storage without data integrity requirements | Select when cost sensitivity outweighs need for enhanced reliability and secure parameter storage |
| M95080-DWDW6TP | Same 8 Kbit capacity and 1.8–5.5 V range, but in SO8N package; identical ID page and ECC features | SO8N footprint requires PCB redesign; same functional behavior and timing specs | Choose for compatibility with legacy SO8 layouts where TSSOP8 board space is constrained |
Compared with AT25080B-SSHL-T, M95080-RMN6TP provides superior data integrity via ECC and secure provisioning via the ID page; compared with M95080-DWDW6TP, it offers identical functionality in a smaller TSSOP8 package, saving 30% board area.
Availability
M95080-RMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics, automotive body control modules, and smart metering systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for M95080-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M95080 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-voltage, high-endurance nonvolatile storage in resource-constrained embedded systems with stringent reliability requirements.
FAQ
What is the function of the HOLD pin on M95080-RMN6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low (with S already low), it places Q in high-impedance and ignores D and C transitions. This allows the host MCU to service higher-priority interrupts while preserving transaction context, resuming seamlessly upon HOLD deassertion.
How does the identification page differ from standard memory pages?
The identification page is a dedicated 32-byte area accessible only via RDID/WRID instructions. Unlike main array pages, it supports the LID instruction to permanently lock itself in read-only mode-preventing overwrite even after WREN and WRITE commands. This makes it ideal for storing immutable device identifiers or cryptographic keys that must survive firmware updates.
Can M95080-RMN6TP operate reliably at 1.8 V during power-up sequences?
Yes. The M95080-R variant guarantees full functionality down to 1.8 V, including reliable instruction execution, write completion, and status register access. Its internal POR circuit activates below the 1.8 V threshold, ensuring deterministic reset and preventing spurious writes during brown-out conditions common in battery-powered or energy-harvesting systems.
What protection mechanisms prevent accidental writes to protected memory blocks?
Accidental writes are prevented by a dual-layer scheme: software protection via BP1/BP0 bits (set by WRSR) defines quarter/half/whole array lock, while hardware protection engages when SRWD=1 and W pin is driven low-freezing BP1/BP0/SRWD bits and rejecting all WRSR commands. Both layers require explicit WREN before any write, adding defense-in-depth against firmware bugs or noise-induced glitches.
M95080-RMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95080-RMN6TP FAQ
1.How can I place an order for M95080-RMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95080-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95080-RMN6TP reliable?
The price and inventory of M95080-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95080-RMN6TP is usually 5 days.
3.What payment methods are accepted for M95080-RMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95080-RMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95080-RMN6TP?
M95080-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95080-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95080-RMN6TP?
For technical support, including M95080-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95080-RMN6TP requirements.
6.How does Aetrix verify that M95080-RMN6TP is sourced from the original manufacturer or authorized distributors?
All M95080-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95080-RMN6TP meets industry standards.
7.What is the process for return or replacement of M95080-RMN6TP?
All M95080-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95080-RMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95080-RMN6TP part is unused and in its original packaging.
Return procedure for M95080-RMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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