STMicroelectronics M95080-WDW6TP
- Part No.:
- M95080-WDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95080-WDW6TP.pdf
- Description:
- IC EEPROM 8KBIT SPI 20MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:6,267
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Product details
Overview
M95080-WDW6TP from STMicroelectronics is an 8-Kbit serial SPI bus EEPROM organized as 1024 × 8 bits, operating from 2.5 V to 5.5 V supply and rated for -40 °C to +85 °C ambient temperature. It supports up to 20 MHz clock frequency, delivers ≤5 ms byte/page write time, and includes ECC x1 error correction per memory byte for enhanced read reliability in industrial control and automotive subsystems.
For engineers reviewing the M95080-WDW6TP datasheet, M95080-WDW6TP pinout, M95080-WDW6TP application, or M95080-WDW6TP equivalent, key selection considerations include its SO8N (150 mil) RoHS-compliant package, hardware/software write protection (W pin + BP1/BP0 bits), identification page lockability, and compatibility with SPI modes CPOL=0/CPHA=0 and CPOL=1/CPHA=1.
Technical Context
The M95080-WDW6TP implements a dedicated SPI interface with edge-triggered sampling: data input (D) latched on rising C edge, data output (Q) valid on falling C edge. Its internal architecture integrates an HV generator, sequencer, ECC x1 logic per byte, and status register with non-volatile BP1/BP0 and SRWD bits.
Write operations require prior WREN instruction and are protected by dual-layer control-software-configurable block protection (quarter/half/whole array) and hardware-enforced Status register lock via W pin and SRWD bit. The device also features built-in power-on reset (POR), hold functionality for transaction pausing, and decoupling-optimized VCC/VSS pin placement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 8 Kbit (1024 × 8 bits), sufficient for firmware parameter storage in microcontroller-based systems |
| Supply voltage | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V logic domains without level shifting |
| Max clock frequency | 20 MHz - enables fast configuration loading in real-time control loops |
| Write cycle time | ≤5 ms per byte or page - reduces system latency during calibration data updates |
| Data retention | 200 years - ensures long-term reliability in unattended infrastructure monitoring |
| Write endurance | 4 million cycles - supports frequent logging in diagnostic or telemetry applications |
| ECC capability | ECC x1 per byte - corrects single-bit errors transparently during reads, improving field failure resilience |
Pinout & Package
Package: SO8N (150 mil width), RoHS-compliant and halogen-free (ECOPACK2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction |
| C | Serial clock | Timing reference; data sampled on rising edge (D), output shifted on falling edge (Q) |
| D | Serial data input | MSB-first input path for instructions, addresses, and write data |
| Q | Serial data output | MSB-first output path for read data and status register contents |
| W | Write protect | Hardware lock for Status register when SRWD = 1; controls BP1/BP0 modifiability |
| HOLD | Hold control | Pauses ongoing SPI transfer without deselecting device; Q goes high-Z while C/D ignored |
| VCC | Supply voltage | 2.5–5.5 V input; requires local 10–100 nF decoupling capacitor |
| VSS | Ground | Signal and supply reference; must be connected directly to system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Identification page (32 bytes) | Separate locked memory region for secure storage of calibration constants or device IDs |
| Block protection granularity | Configurable via BP1/BP0 bits to protect upper quarter (0300h–03FFh), upper half (0200h–03FFh), or full array (0000h–03FFh) |
| Hardware+software write lock | SRWD bit + W pin combination prevents accidental Status register modification in deployed systems |
| SPI mode compatibility | Supports both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 - interoperable with most MCU SPI peripherals |
| Power-on reset (POR) | Prevents spurious writes during power ramp; device remains unresponsive until VCC exceeds POR threshold |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) |
|---|---|
|
Use Scenario: Storing calibrated sensor offsets and actuator thresholds in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Non-volatile parameter repository accessed via SPI during boot and runtime reconfiguration. Use Value: ECC x1 ensures integrity of stored calibration values over decades of operation in electrically noisy environments. |
Use Scenario: Retaining door lock state history, lighting profiles, and seat position memory in automotive BCMs across vehicle lifecycles. IC Role / Device Role / Timing Role: SPI-connected EEPROM providing persistent storage independent of main ECU power domain. Use Value: 4M write cycles and 200-year retention support repeated personalization events without wear-out concerns. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Parameters |
|
Use Scenario: Holding flow-rate calibration coefficients and safety-critical alarm thresholds in Class II medical infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant memory for regulatory-mandated operational parameters. Use Value: Identification page lockability allows permanent write-protection of FDA-required calibration data post-manufacturing. |
Use Scenario: Storing tariff tables, metering constants, and communication keys in ANSI C12.22-compliant smart electricity meters. IC Role / Device Role / Timing Role: Trusted storage element interfaced to metrology SoC via isolated SPI bus. Use Value: Hardware write protection (W pin + SRWD) prevents unauthorized firmware parameter modification during field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25080B-SSHL-T (Microchip) | Same 8-Kbit density and SO8 package, but max clock 20 MHz only at VCC ≥ 2.7 V; no identification page | Lacks dedicated ID page and ECC; suitable where calibration security is not mandated | Select when cost sensitivity outweighs need for ECC or locked ID storage |
| BR24G08FJ-WE2 (ROHM) | 1.7–5.5 V operation, I²C interface (not SPI), 400 kHz standard mode; no HOLD pin or identification page | Requires I²C host and lacks SPI hold functionality; incompatible with existing SPI firmware stack | Choose only for new designs already committed to I²C architecture and lower-speed access |
Compared with AT25080B-SSHL-T and BR24G08FJ-WE2, the M95080-WDW6TP uniquely combines SPI speed (20 MHz), ECC x1, and a lockable identification page - making it optimal for safety-critical or high-integrity parameter storage where interface compatibility and data resilience are jointly required.
Availability
M95080-WDW6TP is available at Aetrix Electronics and suitable for industrial PLC configuration storage, automotive body control modules, medical infusion pump calibration, and smart energy meter firmware parameters requiring stable component supply across multi-year production cycles.
Supply support for M95080-WDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for industrial, automotive, and consumer markets.
The M95080 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, high-reliability non-volatile storage in harsh environments with stringent data integrity requirements.
FAQ
What SPI modes does M95080-WDW6TP support?
The M95080-WDW6TP supports two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of the serial clock (C) and output shifts on the falling edge. The difference lies only in idle clock polarity - C remains low in the first mode and high in the second - ensuring compatibility with most microcontroller SPI peripherals without protocol translation.
How is the identification page protected from accidental overwrite?
The identification page (32 bytes) is protected via the LID instruction, which permanently sets its lock status bit. Once locked, the page becomes read-only and cannot be rewritten even if WREN is issued. This lock is irreversible and survives power cycles, making it suitable for storing immutable device-specific data like calibration certificates or cryptographic keys.
Does M95080-WDW6TP require external pull-up resistors on SPI lines?
Yes - a pull-up resistor (~100 kΩ) on the Chip Select (S) line is recommended to prevent unintended selection during MCU reset or high-impedance states. An external pull-down on the Serial Clock (C) line is advised if the controller may float C during reset, ensuring tSHCH timing compliance and avoiding spurious instruction decoding during power transitions.
What happens during a HOLD condition, and how does it differ from chip deselection?
When HOLD is driven low while S is active (low), SPI communication pauses: Q goes high-Z, and C/D are ignored, but internal state (including address pointer and WEL bit) is preserved. Unlike deselection, HOLD retains context - resuming on HOLD high without reissuing instruction headers. Deselection resets internal logic (except WEL/WIP), making HOLD ideal for interrupting transfers without losing transaction state.
M95080-WDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 8Kbit
- Memory Organization:
- 1K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95080-WDW6TP FAQ
1.How can I place an order for M95080-WDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95080-WDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95080-WDW6TP reliable?
The price and inventory of M95080-WDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95080-WDW6TP is usually 5 days.
3.What payment methods are accepted for M95080-WDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95080-WDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95080-WDW6TP?
M95080-WDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95080-WDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95080-WDW6TP?
For technical support, including M95080-WDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95080-WDW6TP requirements.
6.How does Aetrix verify that M95080-WDW6TP is sourced from the original manufacturer or authorized distributors?
All M95080-WDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95080-WDW6TP meets industry standards.
7.What is the process for return or replacement of M95080-WDW6TP?
All M95080-WDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95080-WDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95080-WDW6TP part is unused and in its original packaging.
Return procedure for M95080-WDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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