STMicroelectronics M95128-DFMC6TG

Overview

M95128-DFMC6TG from STMicroelectronics is a 128-Kbit serial SPI bus EEPROM organized as 16,384 × 8 bits, operating from 1.7 V to 5.5 V over –40 °C to +85 °C. It features 64-byte page write capability (≤5 ms), 4 million write cycles, 200-year data retention, and an additional 64-byte Identification page with permanent lock capability for secure parameter storage in industrial control modules.

For engineers reviewing the M95128-DFMC6TG datasheet, M95128-DFMC6TG pinout, M95128-DFMC6TG application, or M95128-DFMC6TG equivalent, key selection criteria include its 1.7 V minimum supply voltage, hardware-enabled Identification page locking via W and SRWD bits, SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), and ECOPACK2®-compliant UFDFPN8 (2 × 3 mm) package with verified pin mapping.

Technical Context

This device implements a standard SPI interface with dedicated HOLD and WRITE PROTECT inputs for real-time communication suspension and non-volatile block protection configuration. Its internal architecture includes an HV generator, ECC-enabled sense amplifiers, and a status register with WIP, WEL, BP1/BP0, and SRWD bits - enabling precise control of write enable state, memory protection granularity (quarter/half/whole array), and hardware lock enforcement.

The Identification page (64 bytes at fixed address) supports secure provisioning: WRID and LID instructions allow one-time programming and irreversible read-only locking, while RDID and RDLS verify content and lock status. All operations comply with JEDEC-standard SPI timing, including tSHCH hold requirement and MSB-first data framing.

Key Specifications

Pinout & Package

Package: UFDFPN8 (2 × 3 mm), ECOPACK2®-compliant, lead-free, halogen-free, with exposed thermal pad (not electrically connected). Pin 1 marked by chamfered corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT25DF041A-SSHN-B and BR24G128FJ-WE2, M95128-DFMC6TG uniquely combines ultra-low-voltage SPI operation, hardware-enforced ID page locking, and HOLD functionality - making it optimal for safety-critical, interrupt-driven, and secure-edge applications where voltage flexibility and data integrity are non-negotiable.

Availability

M95128-DFMC6TG is available at Aetrix Electronics and suitable for industrial sensor calibration, automotive body control modules, medical infusion pumps, and smart energy meters requiring stable component supply across extended product lifecycles.

Supply support for M95128-DFMC6TG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, MEMS, and non-volatile memory solutions for industrial, automotive, and consumer markets.

M95128-DFMC6TG belongs to ST's serial EEPROM product line, engineered specifically for robust, low-voltage, SPI-based configuration storage in safety- and security-sensitive embedded systems - emphasizing data integrity, long-term reliability, and seamless integration with STM32 and other low-power MCUs.

FAQ

What is the function of the HOLD pin on M95128-DFMC6TG?

The HOLD pin suspends ongoing SPI communication without deselecting the device or resetting internal state. When asserted low while Chip Select (S) is low and Serial Clock (C) is low, it places Q in high-impedance and ignores D and C transitions. This enables host processors to service interrupts or switch tasks mid-transaction, then resume exactly where left off - critical for real-time systems with strict latency budgets.

How does the Identification page differ from main memory?

The Identification page is a dedicated 64-byte memory region accessible only via RDID/WRID/RDLS/LID instructions - not through standard READ/WRITE. Once locked via LID, it becomes permanently read-only, protecting sensitive data like cryptographic keys or calibration fingerprints. Unlike main memory, its address space is fixed and isolated, with separate write-enable and lock logic independent of BP1/BP0 bits.

Can M95128-DFMC6TG operate reliably at 1.7 V?

Yes - M95128-DFMC6TG is fully specified down to 1.7 V VCC, with guaranteed 20 MHz SPI clock operation, 5 ms write times, and correct status register behavior across the full –40 °C to +85 °C range. This is validated in DS1356 Rev 20 AC/DC parameters (Table 10), distinguishing it from M95128-W (2.5 V min) and M95128-R (1.8 V min) variants.

What happens when both W pin and SRWD bit are active?

When SRWD = 1 in the Status Register and the W pin is driven low, the device enters Hardware Protected mode: BP1, BP0, and SRWD bits become read-only, and WRSR instructions are rejected. This prevents software-level reconfiguration of memory protection - a critical safeguard against malware or firmware bugs that could compromise system security or calibration integrity.