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STMicroelectronics M95128-DRDW3TP/K
- Part No.:
- M95128-DRDW3TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95128-DRDW3TP/K.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,078
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Product details
Overview
M95128-DRDW3TP/K from STMicroelectronics is an AEC-Q100 Grade 0 automotive serial EEPROM with 128-Kbit (16-Kbyte) capacity, SPI interface up to 20 MHz, 1.7–5.5 V supply, and extended temperature operation up to +145 °C. It features 64-byte page write, embedded ECC for data integrity, and a lockable 64-byte identification page - deployed in engine control units, battery management systems, and ADAS sensor modules.
For engineers reviewing the M95128-DRDW3TP/K datasheet, M95128-DRDW3TP/K pinout, M95128-DRDW3TP/K application, or M95128-DRDW3TP/K equivalent, key selection criteria include Grade 0 automotive qualification, 145 °C operational capability, hardware/software write protection architecture, and SPI mode compatibility (CPOL=0/CPHA=0 and CPOL=1/CPHA=1).
Technical Context
The device implements a true EEPROM array organized as 256 pages × 64 bytes (16,384 × 8 bits), with embedded error correction code (ECC) logic enhancing bit-level reliability during read operations. The identification page supports permanent lock via LID instruction and stores ST-manufactured ID codes (0x20, 0x00, 0x0E) plus user-defined parameters.
It supports two SPI modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), with data latched on rising C edge and output shifted on falling C edge. Write enable latch (WEL) and status register (SRWD/BP1/BP0) provide hierarchical protection: software-controlled quarter-block lock and hardware-enforced full-array lock via W pin state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16 Kbyte), byte-alterable, organized as 256 × 64-byte pages |
| Interface | SPI-compatible, up to 20 MHz clock, supports CPOL/CPHA = (0,0) and (1,1) |
| Operating temp | −40 °C to +145 °C (Grade 0 AEC-Q100 qualified for under-hood applications) |
| Write endurance | ≥4 million cycles at 25 °C; ≥400,000 cycles at 145 °C |
| Data retention | ≥50 years at 125 °C; ≥100 years at 25 °C |
| Supply voltage | 1.7 V to 5.5 V - enables direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers |
| Page write time | Typically 3.4 ms (max 4 ms) - enables rapid firmware parameter updates without system stall |
| Protection | Hardware W-pin lock + software BP0/BP1 block protection + SRWD status register write disable |
Pinout & Package
Supplied in ECOPACK2-compliant WFDFPN8 (2 mm × 3 mm) package with wettable flank leads for automated optical inspection (AOI) and solder joint reliability in automotive reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C | Serial clock input | Synchronizes all SPI transfers; data latched on rising edge, output shifted on falling edge |
| D | Serial data input | Receives instructions, addresses, and write data (MSB first); high-impedance when deselected |
| Q | Serial data output | Drives read data (MSB first); enters high-impedance state when S is high or HOLD is active |
| S | Chip select input | Edge- and level-sensitive; falling edge initiates command decoding; must be high before first low pulse |
| HOLD | Communication pause control | Halts ongoing SPI transfer without resetting internal address counter; requires S low and C low to activate |
| W | Hardware write protect | Physically disables status register writes when low and SRWD = 1 - prevents accidental configuration changes |
| VCC | Power supply | 1.7–5.5 V tolerant; supports wide-range MCU I/O voltage domains and brown-out resilience |
| VSS | Ground reference | Common return for all signals and internal HV generator; critical for ESD/latch-up robustness |
Key Features
| Feature | Design Value |
|---|---|
| ECC-protected memory array | Embedded error correction logic detects and corrects single-bit errors during read, improving functional safety compliance |
| Lockable identification page | 64-byte dedicated page stores ST device ID and user parameters; permanently locked via LID instruction to prevent tampering |
| Dual protection hierarchy | Software-configurable BP0/BP1 block lock + hardware-enforced SRWD+W pin lock ensures fail-safe write security |
| High-temp endurance | Rated for ≥400,000 write cycles at +145 °C - validated for long-term use in powertrain and battery thermal zones |
| Schmitt-trigger inputs | Input pins (C, D, S, HOLD, W) include noise filtering for reliable operation in electrically noisy automotive environments |
| ECOPACK2 packaging | WFDFPN8 (2 × 3 mm) meets RoHS, halogen-free, and lead-free reflow requirements per AEC-Q200 stress testing |
Applications
| Engine Control Unit (ECU) | Battery Management System (BMS) |
|---|---|
|
Use Scenario: Storing calibration maps, fault logs, and adaptive learning parameters subject to frequent updates across vehicle lifetime. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with deterministic 3.4 ms page write latency and ECC-verified reads during runtime diagnostics. Use Value: Enables zero-latency map switching and secure over-the-air (OTA) parameter updates without risking corruption in high-vibration, high-temperature under-hood conditions. |
Use Scenario: Recording cell voltage history, thermal derating thresholds, and SOC/SOH tracking data in traction battery packs. IC Role / Device Role / Timing Role: High-reliability data logger with 145 °C rating and >400k write cycles - survives repeated thermal cycling near battery cells. Use Value: Guarantees traceable battery health records across 15+ year service life, meeting ISO 26262 ASIL-B data integrity requirements. |
| ADAS Camera Module | Electric Power Steering (EPS) |
|
Use Scenario: Storing lens distortion coefficients, exposure compensation tables, and firmware patch metadata in vision processing units. IC Role / Device Role / Timing Role: Secure boot-time configuration loader with lockable ID page holding camera model and calibration signature. Use Value: Prevents unauthorized firmware modification and ensures optical calibration persistence after power loss or reset events. |
Use Scenario: Retaining torque offset compensation values, motor phase alignment data, and failure event counters in steering assist controllers. IC Role / Device Role / Timing Role: Safety-critical nonvolatile memory with hardware write lock (W pin) preventing unintended overwrite during EMI transients. Use Value: Maintains steering assist accuracy and fault history across ignition cycles while meeting ASIL-C diagnostic coverage targets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4-Mbit SPI Flash (not EEPROM); no built-in ECC; max 85 °C industrial grade | Lacks AEC-Q100 Grade 0 qualification and 145 °C support; unsuitable for under-hood deployment | Select only for non-automotive, lower-temp applications where density > endurance is prioritized |
| BR24G128FJ-WE2 | 128-Kbit I²C EEPROM; 125 °C max; no HOLD pin; no identification page | Slower interface (1 MHz max), no hardware hold function, and missing lockable ID space for secure boot | Use where I²C bus constraints exist and 145 °C operation is not required - e.g., cabin electronics |
Compared with AT25DF041A-SSH-T and BR24G128FJ-WE2, the M95128-DRDW3TP/K uniquely delivers Grade 0 AEC-Q100 validation at +145 °C, integrated ECC, and a cryptographically lockable ID page - making it the only choice for safety-critical, high-temperature automotive data logging where bit integrity and tamper resistance are mandatory.
Availability
M95128-DRDW3TP/K is available at Aetrix Electronics and suitable for engine control units, battery management systems, and ADAS camera modules requiring stable component supply across extended automotive lifecycles.
Supply support for M95128-DRDW3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management solutions, with deep expertise in nonvolatile memory design and AEC-Q100 qualification.
This device belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical data storage in extreme thermal and EMI environments - including powertrain, chassis, and electrification subsystems.
FAQ
What AEC-Q100 grade does M95128-DRDW3TP/K meet, and what does that mean for automotive placement?
M95128-DRDW3TP/K is qualified to AEC-Q100 Grade 0 (−40 °C to +145 °C), the highest reliability tier for automotive ICs. This allows direct mounting in under-hood locations such as engine control units, transmission control modules, and battery junction boxes - where ambient temperatures exceed 125 °C and long-term data integrity is safety-critical.
How does the identification page differ from main memory, and how is it secured?
The identification page is a dedicated 64-byte region separate from the main 128-Kbit array. It contains factory-programmed ST device ID (0x20, 0x00, 0x0E) and user-writable fields. Security is enforced via the LID (Lock Identification) instruction: once executed, the entire page becomes permanently read-only, preventing overwrite or erasure even with WREN enabled.
Can M95128-DRDW3TP/K operate reliably with 1.8 V microcontrollers?
Yes - its 1.7 V to 5.5 V supply range fully covers 1.8 V logic levels. Input thresholds (VIH/VIL) are scaled to match 1.8 V I/O, and Schmitt-trigger inputs reject noise common in low-voltage automotive buses. All SPI timing parameters, including setup/hold times, are guaranteed across this voltage range per DS9007 Rev 9.
What happens if the HOLD pin is asserted during an active write cycle?
HOLD has no effect during an active write cycle (tW). The internal self-timed erase-and-program sequence continues uninterrupted. HOLD only pauses read or command-setup phases - it cannot abort or suspend ongoing writes. After tW completes, the device resumes normal operation, and HOLD remains effective for subsequent transfers.
M95128-DRDW3TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95128-DRDW3TP/K FAQ
1.How can I place an order for M95128-DRDW3TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95128-DRDW3TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95128-DRDW3TP/K reliable?
The price and inventory of M95128-DRDW3TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-DRDW3TP/K is usually 5 days.
3.What payment methods are accepted for M95128-DRDW3TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-DRDW3TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95128-DRDW3TP/K?
M95128-DRDW3TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95128-DRDW3TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95128-DRDW3TP/K?
For technical support, including M95128-DRDW3TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-DRDW3TP/K requirements.
6.How does Aetrix verify that M95128-DRDW3TP/K is sourced from the original manufacturer or authorized distributors?
All M95128-DRDW3TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-DRDW3TP/K meets industry standards.
7.What is the process for return or replacement of M95128-DRDW3TP/K?
All M95128-DRDW3TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95128-DRDW3TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95128-DRDW3TP/K part is unused and in its original packaging.
Return procedure for M95128-DRDW3TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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