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STMicroelectronics M95128-DRMN3TP/K
- Part No.:
- M95128-DRMN3TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95128-DRMN3TP/K.pdf
- Description:
- IC EEPROM 128KBIT SPI 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:5,773
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Product details
Overview
M95128-DRMN3TP/K from STMicroelectronics is an AEC-Q100 Grade 0 automotive EEPROM IC providing 128-Kbit (16-Kbyte) nonvolatile memory with SPI interface, 64-byte page size, and extended temperature operation up to +145 °C. It features embedded ECC logic, a lockable 64-byte identification page, and hardware/software write protection - deployed in engine control units, battery management systems, and ADAS sensor modules for persistent calibration storage.
For engineers reviewing the M95128-DRMN3TP/K datasheet, M95128-DRMN3TP/K pinout, M95128-DRMN3TP/K application, or M95128-DRMN3TP/K equivalent, key selection criteria include its 20 MHz SPI clock support, 4 ms typical page write time, –40 °C to +145 °C operating range, and dual-level write protection (SRWD + W pin) for functional safety-critical firmware parameter retention.
Technical Context
The device implements a true EEPROM array organized as 256 pages × 64 bytes (16384 × 8 bits), with dedicated ECC circuitry correcting single-bit errors and detecting double-bit errors per read cycle. Its SPI interface supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, with data latched on rising C edge and output on falling C edge.
It integrates a status register with WIP (write-in-progress), WEL (write-enable latch), BP0/BP1 (block protect), and SRWD (status register write disable) bits - enabling quarter-block, half-block, or full-array write protection. The HOLD pin allows pausing ongoing transfers without resetting the command sequence, while Schmitt-trigger inputs ensure robust noise immunity in automotive harness environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory capacity | 128 Kbit (16 Kbyte), byte-alterable, organized as 256 × 64-byte pages |
| SPI clock frequency | Up to 20 MHz - enables high-throughput configuration updates in real-time ECU diagnostics |
| Write cycle endurance | ≥ 4 million cycles at 25 °C; ≥ 400,000 cycles at 145 °C - validated for lifetime logging in under-hood applications |
| Data retention | ≥ 50 years at 125 °C; ≥ 100 years at 25 °C - meets ASIL-B long-term data integrity requirements |
| Operating voltage | 1.7 V to 5.5 V - supports wide-input power rails including 3.3 V and 5 V microcontroller interfaces |
| Temperature range | –40 °C to +145 °C (Grade 0, AEC-Q100 qualified) - certified for direct mounting on powertrain ECUs |
| Page write time | Typical 3.4 ms, max 4 ms - enables deterministic firmware update timing in safety-critical bootloaders |
| Identification page | 64-byte lockable area storing ST device ID (0x20, 0x00, 0x0E) and user parameters - permanently read-only after LID command |
Pinout & Package
Supplied in TSSOP8 (169 mil width) package, RoHS-compliant and ECOPACK2-certified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - S (Chip Select) | Active-low device enable | Edge- and level-sensitive; must transition high→low to initiate first command after power-up |
| 2 - W (Write Protect) | Status register hardware lock | When SRWD = 1 and W = low, blocks all WRSR writes - prevents accidental status register corruption |
| 3 - Q (Serial Data Output) | SPI MISO | High-impedance when deselected or during HOLD; outputs MSB-first on falling C edge |
| 4 - VSS | Ground reference | Common return for all signals and VCC; required for stable noise margin and ESD path |
| 5 - VCC | Supply voltage | 1.7–5.5 V input; powers internal HV generator for EEPROM programming and ECC logic |
| 6 - C (Serial Clock) | SPI clock input | Drives internal timing; supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes with Schmitt-trigger input |
| 7 - D (Serial Data Input) | SPI MOSI | Latches instruction, address, and data on rising C edge; MSB-first protocol alignment |
| 8 - HOLD | Communication pause control | Pauses active SPI transfer without deselecting; requires S = low and C = low to activate |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects double-bit errors per read access - eliminates need for external error-handling firmware |
| Lockable identification page | 64-byte area storing factory ID and user data; permanently read-only after LID command - secures calibration constants against overwrite |
| Dual write protection | Software-configurable BP0/BP1 block locks + hardware-enforced SRWD/W pin lock - satisfies ISO 26262 ASIL-B fault containment |
| Extended temperature endurance | Validated operation and write cycling at +145 °C - enables placement in proximity to power semiconductors without derating |
| Fast page write | 3.4 ms typical self-timed write cycle - reduces bootloader latency during over-the-air (OTA) firmware updates |
| Noise-immune inputs | Schmitt-trigger thresholds on S, C, D, HOLD, W - rejects >1 ns glitches common in 12 V automotive harnesses |
Applications
| Engine Control Unit (ECU) | Battery Management System (BMS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim values, knock sensor learning offsets, and cold-start enrichment tables across ignition cycles. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed retention during 15-year vehicle lifecycle and repeated thermal cycling. Use Value: Enables closed-loop engine optimization without requiring external backup power or supercapacitors - reducing BOM cost and board space. |
Use Scenario: Retaining cell balancing history, SOC/SOH calibration coefficients, and fault log timestamps in high-temperature battery packs. IC Role / Device Role / Timing Role: High-reliability EEPROM interfacing directly with BMS MCU via SPI, surviving 145 °C ambient near Li-ion cells. Use Value: Eliminates need for redundant memory or external temperature compensation - simplifying ASIL-D diagnostic coverage. |
| ADAS Camera Module | Electric Power Steering (EPS) |
|
Use Scenario: Holding lens focus calibration, ISP gain tables, and thermal drift compensation profiles updated during factory test and field OTA updates. IC Role / Device Role / Timing Role: Secure, lockable memory for camera-specific parameters - protected against unauthorized modification via SRWD+W pin lock. Use Value: Meets UNECE R155 software update security requirements by preventing tampering with vision system calibration data. |
Use Scenario: Recording torque sensor zero-point drift, motor phase resistance changes, and assist map versioning over vehicle lifetime. IC Role / Device Role / Timing Role: AEC-Q100 Grade 0 EEPROM co-located with EPS MCU for real-time parameter persistence during 10,000+ steering cycles/year. Use Value: Ensures consistent steering feel and responsiveness without recalibration visits - improving customer satisfaction and warranty cost control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-MAHN-T | 4-Mbit SPI Flash (not EEPROM); no built-in ECC; 100k write cycles at 85 °C | Lacks byte-alterability and lockable ID page; requires external wear leveling | Select only if code storage dominates over parameter logging and ECC is handled in firmware |
| BR24G128FJ-WE2 | I²C interface (not SPI); 128 Kbit EEPROM; AEC-Q100 Grade 2 (–40 °C to +105 °C); no HOLD pin | Lower temperature rating; incompatible bus protocol; no communication pause capability | Choose only for I²C-based legacy designs where +105 °C suffices and HOLD is not required |
Compared with AT25DF041A-MAHN-T and BR24G128FJ-WE2, M95128-DRMN3TP/K uniquely combines SPI speed (20 MHz), Grade 0 temperature rating (+145 °C), embedded ECC, and lockable ID page - making it the only drop-in solution for ASIL-B parameter storage in next-generation powertrain and ADAS modules.
Availability
M95128-DRMN3TP/K is available at Aetrix Electronics and suitable for engine control units, battery management systems, and ADAS camera modules requiring stable component supply across extended automotive lifecycles.
Supply support for M95128-DRMN3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management solutions, with over 40 years of microelectronics innovation and ISO/TS 16949-certified manufacturing.
This device belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for functional safety-critical data retention in harsh under-hood and chassis-mounted electronic control units.
FAQ
What is the maximum SPI clock frequency supported by M95128-DRMN3TP/K?
The device supports up to 20 MHz SPI clock frequency across its full operating voltage (1.7–5.5 V) and temperature (–40 °C to +145 °C) range. This enables sub-100 µs instruction response times and efficient bulk reads/writes - critical for time-constrained bootloader operations in automotive ECUs.
How does the identification page differ from main memory, and how is it locked?
The 64-byte identification page resides separately from the main 128-Kbit array and contains ST's device ID (0x20, 0x00, 0x0E) plus user-defined fields. It is locked permanently in read-only mode using the LID instruction - after which RDID remains functional but WRID and LID commands are rejected, ensuring calibration data immutability.
Can M95128-DRMN3TP/K operate reliably at +145 °C during write cycles?
Yes - the device is AEC-Q100 Grade 0 qualified with verified write endurance of ≥400,000 cycles and data retention ≥50 years at +145 °C. Its internal charge pump and ECC logic are thermally characterized to maintain timing and error correction integrity throughout the full temperature range.
What happens if the HOLD pin is asserted during an active write cycle?
HOLD has no effect during an active write cycle (tW): the internal self-timed erase-and-program sequence continues uninterrupted. HOLD only pauses read/write command transfers - not ongoing EEPROM programming - ensuring data integrity is never compromised by external hold requests.
M95128-DRMN3TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95128-DRMN3TP/K FAQ
1.How can I place an order for M95128-DRMN3TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95128-DRMN3TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95128-DRMN3TP/K reliable?
The price and inventory of M95128-DRMN3TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-DRMN3TP/K is usually 5 days.
3.What payment methods are accepted for M95128-DRMN3TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-DRMN3TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95128-DRMN3TP/K?
M95128-DRMN3TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95128-DRMN3TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95128-DRMN3TP/K?
For technical support, including M95128-DRMN3TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-DRMN3TP/K requirements.
6.How does Aetrix verify that M95128-DRMN3TP/K is sourced from the original manufacturer or authorized distributors?
All M95128-DRMN3TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-DRMN3TP/K meets industry standards.
7.What is the process for return or replacement of M95128-DRMN3TP/K?
All M95128-DRMN3TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95128-DRMN3TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95128-DRMN3TP/K part is unused and in its original packaging.
Return procedure for M95128-DRMN3TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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