STMicroelectronics M95128-DRMN8TP/K
- Part No.:
- M95128-DRMN8TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95128-DRMN8TP/K.pdf
- Description:
- IC EEPROM 128KBIT SPI 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:12,082
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Product details
Overview
M95128-DRMN8TP/K from STMicroelectronics is a 128-Kbit serial SPI EEPROM with 16 Kbytes memory organized in 256 × 64-byte pages, rated for operation up to 105 °C and supporting 20 MHz clock at VCC ≥ 4.5 V, featuring embedded ECC logic, an additional lockable 64-byte Identification Page, and AEC-Q100 Grade 2 qualification for automotive use.
For engineers reviewing the M95128-DRMN8TP/K datasheet, M95128-DRMN8TP/K pinout, M95128-DRMN8TP/K application, or M95128-DRMN8TP/K equivalent, this device is selected for high-reliability nonvolatile storage in constrained thermal environments requiring byte-alterable memory, hardware write protection, and SPI-compatible timing compliance across extended voltage (1.7–5.5 V) and temperature ranges.
Technical Context
The M95128-DRMN8TP/K implements a true EEPROM array with built-in Error Correction Code logic that enhances data integrity during read operations across temperature extremes. Its SPI interface supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, with input latching on rising clock edge and output shifting on falling edge - ensuring compatibility with standard microcontroller peripherals.
It features dual-layer write protection: non-volatile Block Protect bits (BP1/BP0) enabling 1/4, 1/2, or full-memory locking, plus SRWD-bit + W-pin coupling for Status Register write disable. The dedicated 64-byte Identification Page supports factory-programmed device ID and user-configurable parameters that can be permanently locked in read-only mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16 Kbytes), organized as 256 pages × 64 bytes - enables efficient page-write operations without block erasure overhead. |
| Max clock frequency | 20 MHz at VCC ≥ 4.5 V - supports high-throughput firmware parameter updates in real-time systems. |
| Operating temperature | −40 °C to +105 °C - qualified per AEC-Q100 Grade 2 for under-hood automotive modules and industrial controllers. |
| Write endurance | 900 k cycles at 105 °C - ensures reliable field calibration storage over product lifetime in thermally stressed applications. |
| Data retention | 50+ years at 105 °C - guarantees long-term integrity of safety-critical configuration data without refresh. |
| Supply voltage range | 1.7 V to 5.5 V - allows direct interfacing with 1.8 V, 3.3 V, and 5 V host systems without level-shifting. |
| ESD protection | 4000 V HBM - provides robustness against handling and board-level electrostatic discharge events. |
Pinout & Package
Package: SO8 (MN), 150 mil width, RoHS-compliant and halogen-free ECOPACK2®.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip Select | Active-low enable signal; falling edge initiates command decoding and must remain low throughout instruction execution. |
| C | Serial Clock | Input clock synchronizing all SPI transfers; data latched on rising edge, output shifted on falling edge. |
| D | Serial Data Input | Input for instructions, addresses, and write data; MSB-first, sampled on rising C edge. |
| Q | Serial Data Output | Output for read data and status bits; high-impedance when S is high or during Hold mode. |
| W | Write Protect | Hardware control pin enabling/disabling Status Register writes when SRWD = 1 - critical for permanent protection setup. |
| HOLD | Hold | Pauses ongoing SPI communication without deselecting device; requires C low to activate/deactivate cleanly. |
| VSS | Ground | Reference node for all digital and analog signals; must be low-impedance connection to minimize noise coupling. |
| VCC | Supply Voltage | Power input (1.7–5.5 V); internal voltage regulator ensures stable core operation across full voltage range. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects double-bit errors in memory reads - eliminates need for external error-handling firmware. |
| Identification Page | 64-byte dedicated area with factory-programmed ST device ID and user-writable fields, lockable to read-only via LID instruction. |
| Flexible write protection | Configurable via BP1/BP0 bits: protect upper quarter (3000h–3FFFh), upper half (2000h–3FFFh), or entire memory including ID page. |
| Schmitt trigger inputs | Applied to S, C, D, HOLD, and W pins - rejects noise spikes and ensures clean signal recognition in electrically noisy automotive environments. |
| Short write cycle time | ≤4 ms for both byte and page writes - reduces system latency during parameter saves and enables deterministic response in time-critical tasks. |
Applications
| Automotive Body Control Module | Industrial PLC Configuration Storage |
|---|---|
|
Use Scenario: Storing calibrated sensor offsets, actuator trim values, and fault history logs in engine control units exposed to under-hood temperatures up to 105 °C. IC Role / Device Role / Timing Role: Nonvolatile configuration register providing byte-alterable, ECC-protected storage accessible via SPI during runtime or power-up initialization. Use Value: Eliminates need for external error-checking logic while maintaining AEC-Q100 compliance and 50-year data retention at peak operating temperature. |
Use Scenario: Holding I/O mapping tables, PID tuning parameters, and firmware update metadata in programmable logic controllers deployed in factory automation cabinets. IC Role / Device Role / Timing Role: SPI-connected persistent memory used for field-updatable system configuration with hardware-enforced write protection against accidental overwrite. Use Value: Enables secure, version-controlled parameter management across production batches using the lockable Identification Page for revision tracking. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Parameters |
|
Use Scenario: Retaining dose calibration coefficients, motor step counts, and usage audit logs in battery-powered infusion pumps requiring long-term reliability and regulatory traceability. IC Role / Device Role / Timing Role: Safety-critical nonvolatile memory storing FDA-mandated calibration data with permanent read-only locking capability after final validation. Use Value: Supports ISO 13485 compliance through tamper-evident parameter locking and 900 k write cycles at elevated ambient temperatures. |
Use Scenario: Storing tariff schedules, metering constants, and cryptographic keys in utility-grade smart meters operating continuously in outdoor enclosures. IC Role / Device Role / Timing Role: High-endurance EEPROM interfaced to metrology SoC via SPI, providing secure, temperature-stable storage for revenue-critical parameters. Use Value: Delivers 5.5 V tolerance and 20 MHz speed for fast key loading during secure boot, with ECC ensuring integrity of billing algorithms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4-Mbit NOR flash with sector erase; no ECC; max 85 °C rating; lacks Identification Page and BP granularity. | Requires software-managed wear leveling and external error detection; unsuitable for AEC-Q100 Grade 2 or >85 °C continuous operation. | Select only if higher density and lower cost outweigh need for ECC, extended temp, and hardware write protection. |
| BR24G128FJ-WE2 | 128-Kbit I²C EEPROM; 105 °C rated; no Identification Page; 1 MHz max clock; no SRWD/W-pin coupling. | Limited to I²C bus topology; slower write throughput; lacks SPI timing flexibility and dual-layer protection scheme. | Prefer for space-constrained designs where I²C is already dominant and 20 MHz SPI bandwidth is unnecessary. |
Compared with AT25DF041A-SSH-T and BR24G128FJ-WE2, the M95128-DRMN8TP/K uniquely combines AEC-Q100 Grade 2 qualification, embedded ECC, 20 MHz SPI speed, and hardware-lockable Identification Page - making it the only choice for safety-aware, thermally demanding, and high-integrity parameter storage.
Availability
M95128-DRMN8TP/K is available at Aetrix Electronics and suitable for automotive body control modules, industrial PLCs, medical infusion pumps, and smart energy meters requiring stable component supply, long-term lifecycle support, and guaranteed ECOPACK2® compliance.
Supply support for M95128-DRMN8TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management solutions, with broad portfolio coverage from microcontrollers to analog and memory devices.
The M95128-DRMN8TP/K belongs to ST's automotive-qualified serial EEPROM product line, designed specifically for mission-critical nonvolatile storage in harsh thermal and electrical environments where data integrity and long-term reliability are mandatory.
FAQ
What is the purpose of the Identification Page and how is it secured?
The Identification Page is a dedicated 64-byte memory region containing three factory-programmed ST device ID bytes followed by user-configurable fields. It can be written using the WRID instruction and permanently locked to read-only mode via the LID instruction - preventing further modification while preserving read access for calibration verification or firmware version checks.
How does the SRWD bit interact with the W pin to control Status Register writes?
When SRWD = 0, the Status Register is always writable regardless of W pin state. When SRWD = 1, writing the Status Register is allowed only if W is driven high; if W is low, all WRSR attempts are discarded and BP1/BP0/SRWD bits become frozen until W is pulled high - enabling irreversible protection of memory block settings in production.
Can this EEPROM operate reliably at 105 °C for extended periods?
Yes - the M95128-DRMN8TP/K is fully characterized and qualified for continuous operation at 105 °C, with 900,000 write cycles and >50 years of data retention specified at that temperature. It meets AEC-Q100 Grade 2 requirements, confirming suitability for under-hood automotive and industrial control applications.
What SPI modes does the device support and how is clock polarity handled?
The device supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes only. In both cases, input data is latched on the rising edge of C and output data appears after the falling edge. The difference lies in idle clock state: C remains low in CPOL=0 mode and high in CPOL=1 mode - allowing seamless integration with common MCU SPI peripherals.
M95128-DRMN8TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
M95128-DRMN8TP/K FAQ
1.How can I place an order for M95128-DRMN8TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95128-DRMN8TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95128-DRMN8TP/K reliable?
The price and inventory of M95128-DRMN8TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-DRMN8TP/K is usually 5 days.
3.What payment methods are accepted for M95128-DRMN8TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-DRMN8TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95128-DRMN8TP/K?
M95128-DRMN8TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95128-DRMN8TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95128-DRMN8TP/K?
For technical support, including M95128-DRMN8TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-DRMN8TP/K requirements.
6.How does Aetrix verify that M95128-DRMN8TP/K is sourced from the original manufacturer or authorized distributors?
All M95128-DRMN8TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-DRMN8TP/K meets industry standards.
7.What is the process for return or replacement of M95128-DRMN8TP/K?
All M95128-DRMN8TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95128-DRMN8TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95128-DRMN8TP/K part is unused and in its original packaging.
Return procedure for M95128-DRMN8TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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