My Inquiry
My Account
STMicroelectronics M95128-DWDW4TP/K
- Part No.:
- M95128-DWDW4TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95128-DWDW4TP/K.pdf
- Description:
- IC EEPROM 128KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,174
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95128-DWDW4TP/K from STMicroelectronics is an AEC-Q100 Grade 0 qualified 128-Kbit SPI serial EEPROM designed for automotive powertrain and body control modules requiring nonvolatile memory with extended temperature operation up to +145 °C. It delivers 64-byte page writes in ≤4 ms, supports 1.7–5.5 V supply, includes embedded ECC, and features a lockable 64-byte identification page for device authentication and parameter storage.
For engineers reviewing the M95128-DWDW4TP/K datasheet, M95128-DWDW4TP/K pinout, M95128-DWDW4TP/K application, or M95128-DWDW4TP/K equivalent, key selection criteria include automotive-grade reliability (AEC-Q100 Grade 0), high-temperature endurance (+145 °C), SPI clock support up to 20 MHz, hardware/software write protection granularity, and identification page locking capability.
Technical Context
This EEPROM implements a true serial SPI interface compliant with CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, using edge- and level-sensitive chip select (S) for robust command initiation after power-up. The internal architecture integrates ECC logic across the 16,384 × 8-bit array, enabling automatic bit error correction during read operations without host intervention.
It features dual-layer write protection: software-configurable quarter-block protection via BP1/BP0 bits in the status register, and hardware-enforced full-array protection via the W pin combined with SRWD bit. The HOLD pin enables communication pause without bus reinitialization, preserving internal state during microcontroller interrupts or low-power transitions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16 Kbyte), organized as 256 pages × 64 bytes - enables efficient firmware patching and calibration data storage in constrained automotive ECUs. |
| Operating temperature | −40 °C to +145 °C (Grade 0) - certified for under-hood applications including engine control units and transmission control modules. |
| SPI clock frequency | Up to 20 MHz - supports fast configuration loading and real-time parameter updates in time-critical systems. |
| Write cycle endurance | ≥4 million cycles at 25 °C; ≥0.4 million at 145 °C - ensures long-term reliability in high-thermal-stress automotive deployments. |
| Data retention | ≥50 years at 125 °C; ≥100 years at 25 °C - guarantees persistent storage of safety-critical calibration and diagnostic logs over vehicle lifetime. |
| Supply voltage | 1.7 V to 5.5 V - compatible with 3.3 V and 5 V microcontroller I/O domains and tolerant of automotive battery transients. |
| Identification page | 64-byte lockable page - stores ST device ID (0x20, 0x00, 0x0E) and user parameters; once locked, prevents overwrite while allowing read access. |
Pinout & Package
Supplied in WFDFPN8 (2 mm × 3 mm, 0.5 mm pitch) package - ultra-compact, thermally enhanced, ECOPACK2-compliant for high-density automotive PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C | Serial clock input | Synchronizes all SPI transfers; latches D on rising edge, drives Q on falling edge; supports both CPOL/CPHA modes. |
| D | Serial data input | Receives instructions, addresses, and write data (MSB-first); high-impedance when not selected. |
| Q | Serial data output | Drives read data (MSB-first) during active READ/RDSR/RDID; enters high-Z when S is high or HOLD is asserted. |
| S | Chip select input | Edge- and level-sensitive enable: falling edge initiates command decoding; high state deselects device and disables Q. |
| HOLD | Communication hold input | Pauses ongoing SPI transfer without resetting internal address counter or clock phase; requires S low and C low to activate. |
| W | Hardware write protect | Controls SRWD-based status register writeability: W low + SRWD = 1 permanently locks BP/SRWD bits until W is raised. |
| VCC | Power supply | 1.7–5.5 V input; powers internal HV generator for EEPROM programming; decoupling capacitor required per layout guidelines. |
| VSS | Ground reference | Common return for all signals and VCC; must be connected directly to PCB ground plane for noise immunity and ESD robustness. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects double-bit errors in real time during memory reads - eliminates need for external checksum validation in safety-critical firmware storage. |
| Lockable identification page | 64-byte dedicated area storing factory-programmed ST ID and user data; LID instruction permanently disables writes while preserving read access - enables secure device binding and calibration traceability. |
| Schmitt-trigger inputs | All digital inputs (C, D, S, HOLD, W) feature hysteresis - rejects noise spikes up to 30% VCC, ensuring reliable operation in electrically noisy automotive environments. |
| Enhanced ESD protection | 4 kV HBM ESD rating - exceeds AEC-Q100 requirements and withstands handling and system-level transients without latch-up or parametric shift. |
| Flexible write protection | Combines software-selectable block protection (BP1/BP0) with hardware-enforced full-array lock (W + SRWD) - allows selective firmware update zones while safeguarding boot code and security keys. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim tables, knock sensor learning values, and emission calibration maps that persist across ignition cycles and survive battery disconnects. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfacing directly with MCU's SPI peripheral; accessed during startup and runtime for closed-loop control parameter lookup. Use Value: Enables self-learning engine behavior over vehicle lifetime while meeting ISO 26262 ASIL-B data integrity requirements via ECC and write-cycle endurance at 145 °C. |
Use Scenario: Retaining camera calibration offsets, radar fusion coefficients, and sensor fusion metadata across power cycles in front-facing ADAS cameras and radar modules. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for safety-critical calibration data; accessed during sensor initialization and periodic recalibration routines. Use Value: Guarantees consistent perception accuracy by preserving factory and field-updated calibration parameters under extreme thermal cycling and vibration conditions. |
| Electric Power Steering (EPS) | Body Control Module (BCM) |
|
Use Scenario: Holding torque assist profiles, steering angle offset compensation, and motor phase alignment data used during EPS motor control loop execution. IC Role / Device Role / Timing Role: High-reliability EEPROM co-located with EPS MCU; accessed during boot and dynamically updated during vehicle service mode. Use Value: Ensures precise steering feel and responsiveness by maintaining calibrated assist curves even after extended high-temperature operation (>125 °C under hood). |
Use Scenario: Storing door lock/unlock patterns, window auto-up/down positions, mirror fold/unfold settings, and lighting configuration preferences per driver profile. IC Role / Device Role / Timing Role: User preference memory interfaced via low-speed SPI; written infrequently but read on every vehicle power-on event. Use Value: Delivers personalized vehicle experience with >100-year data retention at cabin temperatures, eliminating need for backup batteries or supercapacitors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-MAHN-T | 4-Mbit SPI Flash (not EEPROM); no built-in ECC; max temp +105 °C; lacks identification page and HOLD pin. | Requires external wear leveling and error correction; unsuitable for ASIL-B calibration storage or high-temp under-hood use. | Select only for cost-sensitive, non-safety firmware storage where ECC and >125 °C operation are not required. |
| BR24G128FJ-WE2 | 128-Kbit I²C EEPROM; AEC-Q100 Grade 2 (−40 °C to +105 °C); no HOLD or identification page; slower 1 MHz max clock. | Limited to cabin-located modules; incompatible with SPI-based MCU peripherals; no hardware-assisted write protection granularity. | Choose only when I²C interface is mandated and operating temperature remains below 105 °C. |
Compared with AT25DF041A-MAHN-T and BR24G128FJ-WE2, the M95128-DWDW4TP/K uniquely combines AEC-Q100 Grade 0 qualification, embedded ECC, lockable ID page, and 20 MHz SPI speed - making it the sole option for safety-critical, high-temperature automotive EEPROM applications demanding guaranteed data integrity and long-term reliability.
Availability
M95128-DWDW4TP/K is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, electric power steering systems, and body control modules requiring stable component supply across extended automotive lifecycles.
Supply support for M95128-DWDW4TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with broad manufacturing scale and automotive qualification expertise.
The M95128 series belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical nonvolatile storage in harsh-temperature automotive subsystems where data integrity, longevity, and AEC-Q100 compliance are mandatory.
FAQ
What is the maximum operating temperature for M95128-DWDW4TP/K?
The M95128-DWDW4TP/K is rated for continuous operation from −40 °C to +145 °C and is AEC-Q100 Grade 0 qualified. This specification is verified per DS9007 Rev 9, with write endurance and data retention performance validated at 145 °C. It is intended for under-hood applications such as engine control units and transmission control modules where ambient temperatures exceed 125 °C.
Does M95128-DWDW4TP/K support SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, the device supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In both modes, data are latched on the rising edge of C and shifted out on the falling edge. The difference lies only in idle clock polarity: C remains high in Mode 3 standby, enabling interoperability with MCUs configured for either standard. This is explicitly confirmed in Section 3.2 of DS9007 Rev 9.
How is the identification page protected from accidental overwrite?
The 64-byte identification page is protected in two stages: first, software write protection is enabled via the LID instruction, which permanently sets a lock bit; second, hardware protection is enforced by driving the W pin low while SRWD = 1. Once locked, the page is read-only - no subsequent WRITE or WRID commands will modify its contents, and RDID continues to return stored data. This dual mechanism is detailed in Sections 3.5 and 3.4.2 of DS9007 Rev 9.
What happens to the internal address counter during HOLD activation?
When HOLD is asserted (low) while S is low and C is low, the internal address counter freezes exactly at its current value - neither incrementing nor resetting. Upon deassertion of HOLD (high), the device resumes communication from the same address and bit position where it paused, preserving full SPI transaction state. This behavior is defined in Figure 4 and Section 3.3 of DS9007 Rev 9 and enables deterministic interrupt handling in real-time automotive firmware.
M95128-DWDW4TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 145°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95128-DWDW4TP/K FAQ
1.How can I place an order for M95128-DWDW4TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95128-DWDW4TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95128-DWDW4TP/K reliable?
The price and inventory of M95128-DWDW4TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-DWDW4TP/K is usually 5 days.
3.What payment methods are accepted for M95128-DWDW4TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-DWDW4TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95128-DWDW4TP/K?
M95128-DWDW4TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95128-DWDW4TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95128-DWDW4TP/K?
For technical support, including M95128-DWDW4TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-DWDW4TP/K requirements.
6.How does Aetrix verify that M95128-DWDW4TP/K is sourced from the original manufacturer or authorized distributors?
All M95128-DWDW4TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-DWDW4TP/K meets industry standards.
7.What is the process for return or replacement of M95128-DWDW4TP/K?
All M95128-DWDW4TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95128-DWDW4TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95128-DWDW4TP/K part is unused and in its original packaging.
Return procedure for M95128-DWDW4TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95128-DWDW4TP/K Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
