STMicroelectronics M95128-RMC6TG

Overview

M95128-RMC6TG from STMicroelectronics is a 128-Kbit serial SPI bus EEPROM organized as 16,384 × 8 bits, operating from 1.8 V to 5.5 V supply voltage with 20 MHz clock support. It features 64-byte page write capability, 4 million write cycles, 200-year data retention, and hardware/software write protection including quarter/half/whole array lock. Used in industrial sensor calibration storage and embedded system configuration backup.

For engineers reviewing the M95128-RMC6TG datasheet, M95128-RMC6TG pinout, M95128-RMC6TG application, or M95128-RMC6TG equivalent, this device delivers deterministic SPI timing (CPOL=0/1, CPHA=0/1), high-ESD robustness, and identification-page locking for secure parameter storage in resource-constrained designs.

Technical Context

The M95128-RMC6TG implements a standard SPI interface with dual-mode clock polarity support (CPOL=0/1, CPHA=0/1), where input data is latched on the rising edge of C and output data transitions on the falling edge. Its internal HV generator enables byte/page programming without external high-voltage sources.

Memory organization includes a dedicated 64-byte Identification page-accessible only via RDID/WRID instructions-that supports permanent read-only locking via LID command. Block protection is controlled by non-volatile BP1/BP0 bits in the Status register, enabling configurable software write lock of upper quarter (3000h–3FFFh), upper half (2000h–3FFFh), or full memory + ID page.

Key Specifications

Pinout & Package

Package: TSSOP8 (169 mil width), ECOPACK2®-compliant, 8-pin surface-mount with standard pin 1 marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT25128B-SSHL-T and BR24G128FJ-WE2, the M95128-RMC6TG uniquely combines SPI speed, low-voltage operation, and cryptographically relevant ID-page locking-making it optimal for safety- or security-aware embedded systems requiring both performance and assured data integrity.

Availability

M95128-RMC6TG is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, and automotive body control modules requiring stable component supply across extended product lifecycles.

Supply support for M95128-RMC6TG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.

The M95128-R series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, high-reliability nonvolatile storage in space- and power-constrained embedded systems with stringent data integrity requirements.

FAQ

What SPI modes does M95128-RMC6TG support?

The M95128-RMC6TG supports exactly two SPI modes: (CPOL = 0, CPHA = 0) and (CPOL = 1, CPHA = 1). In both, data is latched on the rising edge of C and output changes on the falling edge. It does not support (CPOL = 0, CPHA = 1) or (CPOL = 1, CPHA = 0), as confirmed in Section 4.1 of DS1356 Rev 20.

How is the Identification page accessed and secured?

The Identification page (64 bytes) is accessed exclusively via RDID and WRID instructions (opcodes 10000011 and 10000010), not standard READ/WRITE. It is secured by the LID instruction, which permanently sets its lock bit; once locked, only RDID remains functional, and WRID returns undefined behavior per datasheet Section 6.

What happens if Chip select (S) is deasserted during a HOLD condition?

If S is driven high while HOLD is active, the device resets its internal SPI state machine (except WEL and WIP bits), terminating the current transaction. If a WRITE command was partially received, deasserting S triggers immediate execution of that decoded command, initiating the internal write cycle per Section 5.3 footnote in DS1356 Rev 20.

Can the M95128-RMC6TG operate reliably at 1.8 V with 20 MHz clock?

Yes - the "R" suffix explicitly denotes 1.8 V minimum VCC, and AC timing parameters in Section 9 of DS1356 Rev 20 validate tCH/tCL ≤ 25 ns and tSU/DH ≥ 8 ns at VCC = 1.8 V, supporting full 20 MHz operation without timing margin violation.