Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

STMicroelectronics M95128-RMN6TP

Name: M95128-RMN6TP
Brand: STMicroelectronics
SKU: M95128-RMN6TP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: M95128-RMN6TP

Manufacturer:: STMicroelectronics

Category:: Memory

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: M95128-RMN6TP.pdf

Description:: IC EEPROM 128KBIT SPI 8SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:10,378

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

M95128-RMN6TP from STMicroelectronics is a 128-Kbit serial SPI bus EEPROM organized as 16,384 × 8 bits, operating from 1.8 V to 5.5 V supply voltage with 20 MHz clock support. It features 64-byte page write capability (≤5 ms), 4 million write cycles, 200-year data retention, and hardware/software write protection including quarter/half/whole array lock via BP1/BP0 bits in the Status register. Used in industrial control modules for nonvolatile parameter storage during power loss.

For engineers reviewing the M95128-RMN6TP datasheet, M95128-RMN6TP pinout, M95128-RMN6TP application, or M95128-RMN6TP equivalent, key selection criteria include its 1.8 V minimum V_CC, TSSOP8 (169 mil) package compatibility, Identification page support (64 bytes, lockable), dual SPI mode (CPOL/CPHA = 0/0 or 1/1), and enhanced ESD protection per ECOPACK2® standard.

Technical Context

This EEPROM implements a synchronous serial peripheral interface compliant with SPI modes 0 and 3, using edge-triggered latching: data input (D) sampled on rising C, output (Q) valid on falling C. Internal high-voltage generator enables byte/page programming without external V_PP.

It integrates a nonvolatile Status register with SRWD, BP1/BP0, WEL, and WIP bits - enabling flexible memory protection schemes. The HOLD pin allows pausing ongoing transfers without chip deselection, preserving internal state and clock alignment across multi-master SPI systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	128 Kbit (16 Kbytes), organized as 16384 × 8 bits - supports firmware configuration storage in resource-constrained microcontrollers.
Supply voltage range	1.8 V to 5.5 V - enables direct interfacing with 1.8 V logic families and legacy 3.3 V/5 V systems without level shifters.
Max clock frequency	20 MHz - reduces full-array read time to <13 ms, critical for fast boot-time parameter loading.
Write endurance	4 million cycles - supports daily calibration updates over 10+ years in industrial sensor nodes.
Data retention	200 years at +25 °C - ensures long-term reliability in unattended infrastructure monitoring equipment.
Operating temperature	−40 °C to +85 °C - qualified for deployment in outdoor telecom cabinets and factory-floor PLCs.
Page size	64 bytes - matches typical MCU cache line sizes and minimizes wasted write overhead in small-data updates.

Pinout & Package

TSSOP8 (169 mil width) package per ECOPACK2® standard, 8-pin surface-mount with gull-wing leads, RoHS-compliant and halogen-free.

Pin/Terminal	Circuit Role	Design Meaning
S	Chip select	Active-low enable signal; falling edge required after power-up before first instruction - prevents spurious writes during V_CC ramp.
C	Serial clock	Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q) - supports CPOL/CPHA = 0/0 or 1/1.
D	Serial data input	MSB-first instruction/address/data input path; accepts WREN, WRITE, WRSR, RDID commands - requires stable setup/hold relative to C.
Q	Serial data output	MSB-first read data output; high-impedance when S is high or HOLD is asserted - enables multi-device SPI bus sharing.
W	Write protect	Hardware lock for Status register bits (BP1/BP0/SRWD); low + SRWD=1 enables Hardware Protected mode - prevents accidental reconfiguration of protection settings.
HOLD	Communication hold	Pauses active SPI transfer without resetting internal state; Q goes high-Z, D/C ignored - used for priority interrupt handling in real-time systems.
V_CC	Supply voltage	1.8–5.5 V power rail; requires local 10–100 nF decoupling capacitor - ensures stable internal HV generator operation during write cycles.
V_SS	Ground	Reference for all I/O and internal circuitry; must be low-impedance connection to minimize noise coupling into sensitive analog blocks.

Key Features

Feature	Design Value
Identification page	64-byte dedicated memory block with permanent lock (LID command) - stores calibrated sensor offsets or cryptographic keys immune to field firmware updates.
Flexible write protection	Software-configurable (BP1/BP0) quarter/half/full array lock plus hardware W pin control - enables layered security for bootloader vs. application data partitions.
Power-on reset (POR)	Internal POR circuit holds device inactive until V_CC exceeds threshold - eliminates need for external reset IC in space-constrained designs.
ECOPACK2® packaging	TSSOP8 with halogen-free, RoHS-compliant materials and optimized thermal resistance - meets IPC/JEDEC J-STD-020 moisture sensitivity level 3 (MSL3).
Dual SPI mode support	Native compatibility with both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 - interoperates with diverse MCU families (STM32, PIC, NXP Kinetis) without software abstraction layer.

Applications

Industrial PLC Configuration Storage

Medical Device Calibration Data

Use Scenario: Storing I/O mapping tables and PID tuning parameters in programmable logic controllers that undergo frequent firmware updates but require persistent runtime settings.

IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed via SPI during boot and runtime; uses HOLD to suspend reads during interrupt-driven analog acquisition cycles.

Use Value: Eliminates battery-backed SRAM; 200-year retention ensures parameter integrity across 15+ year product lifecycles without maintenance.

Use Scenario: Retaining factory-calibrated gain/offset coefficients for ECG front-end amplifiers in portable diagnostic devices subject to regulatory audit trails.

IC Role / Device Role / Timing Role: Secure configuration vault; Identification page locked via LID command post-calibration to prevent tampering with traceable calibration records.

Use Value: Meets IEC 62304 Class C software requirements by providing immutable, version-stamped calibration data with hardware-enforced read-only enforcement.

Smart Meter Firmware Patch Log

Automotive Body Control Module Settings

Use Scenario: Logging firmware patch application timestamps and checksums in utility smart meters deployed in remote substations with infrequent maintenance windows.

IC Role / Device Role / Timing Role: Write-intensive event logger; leverages 4M-cycle endurance to record >1000 patch events over 10 years without wear leveling.

Use Value: Enables field-upgrade verification and rollback capability while avoiding complex flash translation layers in cost-sensitive meter SoCs.

Use Scenario: Storing user preferences (seat position, mirror angle, lighting profiles) in automotive body control units where power loss occurs frequently during ignition cycling.

IC Role / Device Role / Timing Role: Low-voltage EEPROM interface; operates down to 1.8 V during cranking transients when battery dips to 6 V, ensuring settings survive cold starts.

Use Value: Guarantees sub-100 ms parameter restore after ignition-on, meeting OEM UI responsiveness requirements without backup capacitors.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT25128B-SSHL-T	1.8–5.5 V supply, 20 MHz max clock, but lacks Identification page and LID/RDID/WRID instructions.	No hardware-lockable calibration storage; unsuitable for regulated medical or metrology use cases requiring immutable parameter archives.	Select when only basic parameter storage is needed and BOM cost is prioritized over security features.
BR24G128FJ-WE2	I²C interface (not SPI), 1.7–5.5 V, 1 MHz max clock, integrated address pins for multi-device addressing.	Requires I²C-capable MCU; slower write throughput limits suitability for high-frequency logging or fast-boot scenarios.	Select for space-constrained designs where I²C bus already exists and SPI pins are unavailable.

Compared with AT25128B-SSHL-T and BR24G128FJ-WE2, M95128-RMN6TP uniquely combines SPI speed, low-voltage operation, and hardware-enforced calibration page locking - making it optimal for safety-critical or audit-trail-sensitive embedded systems where data integrity is non-negotiable.

Availability

M95128-RMN6TP is available at Aetrix Electronics and suitable for industrial automation controllers, portable medical diagnostics, smart utility meters, and automotive body electronics requiring stable component supply across extended production lifecycles.

Supply support for M95128-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.

The M95128 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, SPI-based nonvolatile storage in harsh environments - emphasizing long-term data integrity, wide supply voltage tolerance, and secure configuration management.

FAQ

What is the function of the HOLD pin on M95128-RMN6TP?

The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low during an active transfer, Q goes high-impedance and D/C are ignored, allowing the host MCU to service higher-priority interrupts. Communication resumes transparently upon deassertion, preserving bit alignment and transaction context - essential for deterministic real-time systems.

How does the Identification page differ from main memory in M95128-RMN6TP?

The Identification page is a dedicated 64-byte memory region accessible only via RDID/WRID/LID commands. Unlike main array pages, it supports permanent read-only locking via the LID instruction - once locked, no subsequent WRID or WRITE can modify it. This enables secure storage of calibration constants, device serial numbers, or cryptographic keys that must survive field firmware updates.

Can M95128-RMN6TP operate reliably at 1.8 V while running at 20 MHz?

Yes - the M95128-R variant is explicitly characterized for full functionality (including 20 MHz clock, 5 ms page write, and status register access) across its entire 1.8 V to 5.5 V supply range. DC and AC parameters in DS1356 Rev 20 confirm t_CL, t_CH, t_DS, and t_DH meet specification at V_CC = 1.8 V, enabling direct interface with ultra-low-power 1.8 V MCUs without voltage translation.

What happens if Chip select (S) is driven high mid-transfer on M95128-RMN6TP?

Driving S high mid-transfer terminates the current instruction sequence and places the device in Standby mode. If a WRITE or WRSR command was partially received, the incomplete instruction is discarded and no write occurs. However, if S rises precisely after the eighth bit of a valid WRITE command, the internal write cycle initiates immediately - this behavior is leveraged in standard SPI write protocols to trigger programming without additional handshaking.

M95128-RMN6TP Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 128Kbit

Memory Organization:: 16K x 8

Memory Interface:: SPI

Clock Frequency:: 20 MHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: -

Voltage - Supply:: 1.8V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

M95128-RMN6TP FAQ

1.How can I place an order for M95128-RMN6TP through Aetrix?

Please submit a Request for Quotation (RFQ) for M95128-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M95128-RMN6TP reliable?

The price and inventory of M95128-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-RMN6TP is usually 5 days.

3.What payment methods are accepted for M95128-RMN6TP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-RMN6TP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M95128-RMN6TP?

M95128-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M95128-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M95128-RMN6TP?

For technical support, including M95128-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-RMN6TP requirements.

6.How does Aetrix verify that M95128-RMN6TP is sourced from the original manufacturer or authorized distributors?

All M95128-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-RMN6TP meets industry standards.

7.What is the process for return or replacement of M95128-RMN6TP?

All M95128-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95128-RMN6TP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M95128-RMN6TP part is unused and in its original packaging.

Return procedure for M95128-RMN6TP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…