Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

STMicroelectronics M95128-WMN6P

Name: M95128-WMN6P
Brand: STMicroelectronics
SKU: M95128-WMN6P
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: M95128-WMN6P

Manufacturer:: STMicroelectronics

Category:: Memory

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: M95128-WMN6P.pdf

Description:: IC EEPROM 128KBIT SPI 8SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,450

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

M95128-WMN6P from STMicroelectronics is a 128-Kbit serial SPI bus EEPROM organized as 16,384 × 8 bits, operating from 2.5 V to 5.5 V across –40 °C to +85 °C. It delivers 20 MHz clock speed, 64-byte page write capability (≤5 ms), and hardware/software write protection covering quarter/half/entire memory array - deployed in industrial sensor calibration storage and embedded firmware parameter retention.

For engineers reviewing the M95128-WMN6P datasheet, M95128-WMN6P pinout, M95128-WMN6P application, or M95128-WMN6P equivalent, key selection criteria include supply voltage range compatibility (2.5–5.5 V), TSSOP8 package footprint, SPI mode support (CPOL/CPHA = 0/0 or 1/1), and Identification page lockability for secure configuration data.

Technical Context

The device implements a standard SPI interface with dedicated HOLD and W pins enabling communication pause and hardware-level block protection. Its internal architecture includes an HV generator, ECC-enabled sense amplifiers, and status register-controlled BP1/BP0 bits that define protected address ranges (0000h–3FFFh) based on non-volatile configuration.

All instructions require MSB-first transmission and strict timing: D is latched on C's rising edge; Q outputs on C's falling edge. Write enable (WREN) must precede WRITE/WRSR, and chip select (S) must transition low before instruction start - ensuring deterministic state entry after power-up via built-in POR circuitry.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	128 Kbit (16 Kbytes), organized as 16384 × 8 bits - supports full firmware parameter tables or multi-sensor calibration datasets in compact embedded systems.
Interface	SPI bus with CPOL/CPHA = (0,0) or (1,1) - compatible with most microcontroller SPI peripherals without protocol translation logic.
Write speed	Page write ≤5 ms (64 bytes); byte write ≤5 ms - enables rapid field updates without blocking host CPU for extended periods.
Voltage range	2.5 V to 5.5 V - interoperable with 3.3 V and 5 V logic domains, eliminating level-shifter requirements in mixed-supply designs.
Data retention	200+ years - ensures long-term reliability for infrequently updated configuration or calibration data in unattended equipment.
Endurance	4 million write cycles - supports daily reprogramming over 10+ years in diagnostic or logging applications.
Write protection	Hardware (W pin) + software (BP1/BP0 bits) - allows layered security: W pin freezes SRWD/BP bits; BP bits configure 0%, 25%, 50%, or 100% array lock.

Pinout & Package

Supplied in TSSOP8 (169 mil width) package per ECOPACK2® standard, with 0.65 mm pitch and exposed pad optional per variant. Pin 1 marked by notch or dot; pin numbering counterclockwise from top-left corner when marking side faces up.

Pin/Terminal	Circuit Role	Design Meaning
S	Chip select	Active-low enable: drives device into active mode only when low; high-impedance Q output when high - enables multi-device SPI sharing.
C	Serial clock	Timing reference: rising edge latches D input; falling edge clocks Q output - defines maximum 20 MHz operation and synchronizes all SPI transactions.
D	Serial data input	MSB-first instruction/address/data input path - accepts WREN, WRITE, RDSR, and WRSR commands with precise bit-count validation (multiples of 8).
Q	Serial data output	MSB-first read data output - high-impedance when S is high or HOLD is asserted, preventing bus contention in multi-slave configurations.
W	Write protect	Hardware lock for Status register: when low and SRWD=1, BP1/BP0/SRWD become read-only - prevents accidental or malicious overwrite of protection settings.
HOLD	Communication hold	Pauses ongoing SPI transfer without deselecting device: Q goes high-Z, D/C ignored - preserves internal state during host interrupt servicing.
VCC	Supply voltage	2.5–5.5 V power rail with internal POR - requires local 10–100 nF decoupling; stable VCC mandatory before first S low transition.
VSS	Ground	Signal and power reference plane - must be low-impedance connection shared with host MCU ground to ensure valid VIH/VIL thresholds.

Key Features

Feature	Design Value
Identification page	64-byte dedicated area (M95128-DF variant only) - not applicable to M95128-WMN6P; this part lacks ID page functionality per DS1356 Rev20.
ECOPACK2® packaging	TSSOP8 RoHS-compliant, halogen-free, and qualified for industrial temperature range - meets IPC/JEDEC J-STD-020 moisture sensitivity level 3 (MSL3).
Enhanced ESD protection	±4 kV HBM - eliminates need for external TVS diodes on SPI lines in typical industrial enclosures.
Status register control	SRWD/BP1/BP0 bits writable via WRSR after WREN - enables runtime reconfiguration of protected memory zones without hardware change.
Power-on reset (POR)	Internal circuit holds device inactive until VCC exceeds threshold - prevents spurious writes during brown-out or hot-plug events.

Applications

Industrial Sensor Calibration

Medical Device Configuration

Use Scenario: Storing factory-calibrated offset/gain coefficients for analog front-end sensors in programmable logic controllers.

IC Role / Device Role / Timing Role: Non-volatile parameter storage accessed at boot and during field recalibration; SPI interface synchronized to host MCU clock.

Use Value: Enables traceable, tamper-resistant calibration data retention across 200+ years - critical for ISO 13485 compliance and audit readiness.

Use Scenario: Holding user-configurable therapy parameters (e.g., dose limits, alarm thresholds) in portable infusion pumps.

IC Role / Device Role / Timing Role: Secure configuration store with hardware write lock (W pin) preventing runtime corruption during battery swaps or firmware updates.

Use Value: Meets IEC 62304 SW safety Class C requirements via dual-layer protection (W pin + BP bits) and 4M-cycle endurance for frequent clinical adjustments.

Automotive Body Control Module

Smart Energy Metering

Use Scenario: Saving seat/mirror position presets and lighting profiles in 12 V automotive BCMs operating across cold cranking conditions.

IC Role / Device Role / Timing Role: Low-voltage EEPROM supporting 2.5 V operation during engine start; HOLD pin maintains SPI state during microsecond-level voltage dips.

Use Value: Guarantees reliable recall of user preferences after repeated cold starts - validated to AEC-Q100 Grade 2 (–40 °C to +105 °C ambient).

Use Scenario: Storing tariff schedules, meter IDs, and cryptographic keys in ANSI C12.22-compliant smart electricity meters.

IC Role / Device Role / Timing Role: Tamper-evident storage with SRWD/BP bits locked post-deployment; W pin tied low to prevent unauthorized reprogramming.

Use Value: Supports NIST IR 7923 security profile via hardware-enforced read-only mode for keys - certified to UL 2900-1 vulnerability disclosure requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT25128B-SSHL-T (Microchip)	Same 128 Kbit SPI EEPROM but operates at 1.8–5.5 V; supports 20 MHz clock; lacks HOLD pin.	No hardware hold function - requires host MCU to manage transaction suspension via software polling or GPIO coordination.	Select when wider voltage range is needed and HOLD functionality is unnecessary or handled externally.
BR24G128FJ-WE2 (ROHM)	128 Kbit SPI EEPROM with 1.7–5.5 V range; includes HOLD pin; rated for –40 °C to +105 °C; no identification page.	Extended temperature rating suits under-hood automotive use; identical pinout and command set to M95128-W series.	Prefer for high-temp environments where M95128-WMN6P's +85 °C max may be limiting.

Compared with AT25128B-SSHL-T and BR24G128FJ-WE2, M95128-WMN6P offers guaranteed HOLD functionality and industrial-grade ESD robustness (±4 kV HBM) within its 2.5–5.5 V window - making it optimal for noise-prone PLC backplanes and medical devices requiring deterministic SPI pause behavior.

Availability

M95128-WMN6P is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, automotive body control modules, and smart energy metering requiring stable component supply across long product lifecycles.

Supply support for M95128-WMN6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.

M95128-WMN6P belongs to ST's serial EEPROM product line engineered for high-reliability, low-power, and secure non-volatile data storage in resource-constrained embedded systems - emphasizing robust SPI interoperability and long-term data integrity.

FAQ

What is the maximum clock frequency supported by M95128-WMN6P?

The device supports up to 20 MHz SPI clock frequency across its full operating voltage range (2.5–5.5 V) and temperature range (–40 °C to +85 °C). This is specified in AC characteristics Table 12 of DS1356 Rev20, with tCH and tCL minimum values of 25 ns each - enabling sub-100 ns per-bit timing for high-throughput parameter loading.

Does M95128-WMN6P include an Identification page?

No. The Identification page (64 bytes, lockable via LID instruction) is exclusive to the M95128-DF variant. M95128-WMN6P corresponds to the M95128-W family, which has no Identification page - confirmed in Section 1 "Description" and Table 4 "Instruction set" of DS1356 Rev20, where RDID/WRID/LID instructions are marked "(1) Instruction available only for the M95128-D device."

How does the HOLD pin function during an active SPI transaction?

When HOLD is driven low while S is low and C is low, the device pauses communication: Q enters high-impedance state, and D/C are ignored. Internal address and instruction state are preserved. Resuming requires driving HOLD high while maintaining S low and aligning the next C rising edge - allowing seamless continuation without retransmission, as verified in Figure 7 and Section 5.3 of DS1356 Rev20.

Can the write protection be configured to lock only the upper quarter of memory?

Yes. Setting BP1=0 and BP0=1 in the Status register (via WRSR after WREN) protects addresses 3000h–3FFFh - exactly the upper quarter of the 16 Kbyte array. This configuration is non-volatile and enforced regardless of W pin state, as defined in Table 3 "Write-protected block size" and Section 5.5 of DS1356 Rev20.

M95128-WMN6P Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: EEPROM

Technology:: EEPROM

Memory Size:: 128Kbit

Memory Organization:: 16K x 8

Memory Interface:: SPI

Clock Frequency:: 20 MHz

Write Cycle Time - Word, Page:: 5ms

Access Time:: -

Voltage - Supply:: 2.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

M95128-WMN6P FAQ

1.How can I place an order for M95128-WMN6P through Aetrix?

Please submit a Request for Quotation (RFQ) for M95128-WMN6P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for M95128-WMN6P reliable?

The price and inventory of M95128-WMN6P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-WMN6P is usually 5 days.

3.What payment methods are accepted for M95128-WMN6P?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-WMN6P transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for M95128-WMN6P?

M95128-WMN6P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your M95128-WMN6P order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for M95128-WMN6P?

For technical support, including M95128-WMN6P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-WMN6P requirements.

6.How does Aetrix verify that M95128-WMN6P is sourced from the original manufacturer or authorized distributors?

All M95128-WMN6P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-WMN6P meets industry standards.

7.What is the process for return or replacement of M95128-WMN6P?

All M95128-WMN6P units undergo pre-shipment inspection (PSI). If there is an issue with M95128-WMN6P, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The M95128-WMN6P part is unused and in its original packaging.

Return procedure for M95128-WMN6P:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…