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STMicroelectronics M95128-WMN6TP
- Part No.:
- M95128-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95128-WMN6TP.pdf
- Description:
- IC EEPROM 128KBIT SPI 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:11,653
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Product details
Overview
M95128-WMN6TP from STMicroelectronics is a 128-Kbit serial SPI bus EEPROM organized as 16,384 × 8 bits, operating from 2.5 V to 5.5 V across –40 °C to +85 °C. It supports 20 MHz clock speed, 64-byte page writes completing in ≤5 ms, and offers quarter/half/whole-array write protection via BP1/BP0 bits in its Status register. Used for firmware parameter storage in industrial controllers where nonvolatile, field-upgradable configuration data must survive >4 million write cycles and >200 years of retention.
For engineers reviewing the M95128-WMN6TP datasheet, M95128-WMN6TP pinout, M95128-WMN6TP application, or M95128-WMN6TP equivalent, key selection considerations include supply voltage range (2.5–5.5 V), SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), identification page lockability, hold functionality for bus arbitration, and ECOPACK2®-compliant TSSOP8 packaging with 169 mil width.
Technical Context
This EEPROM implements a synchronous SPI interface with dedicated HOLD and W pins enabling real-time bus pause and hardware-based status register protection. Its internal architecture includes an HV generator, ECC-enabled sense amplifiers, and page latches supporting atomic 64-byte writes without external timing control.
The device integrates power-on reset (POR) logic that prevents instruction execution until VCC exceeds threshold, and supports dual-level write protection: software-configurable block protection (BP1/BP0) plus hardware-enforced SRWD+W locking of nonvolatile status bits - ensuring critical configuration pages remain immutable after field deployment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (16 Kbytes), organized as 16384 × 8 bits - sufficient for bootloader config, calibration tables, or device identity storage in resource-constrained systems. |
| Page size | 64 bytes - enables efficient partial updates without erasing full sectors; matches typical MCU cache line or packet buffer sizes. |
| Write time | ≤5 ms per byte or per page - eliminates need for polling delays longer than 5 ms, simplifying firmware timeout handling. |
| Supply voltage | 2.5 V to 5.5 V - interoperable with 3.3 V and 5 V logic domains without level shifters. |
| Clock speed | Up to 20 MHz - supports high-throughput configuration loading in boot sequences or diagnostics. |
| Data retention | >200 years - guarantees long-term integrity of factory-set parameters or field-calibrated coefficients. |
| Endurance | >4 million write cycles - withstands frequent logging or runtime tuning in industrial HMI or sensor nodes. |
Pinout & Package
Package: TSSOP8 (169 mil width), ECOPACK2®-compliant, surface-mount, 8-pin exposed-pad variant not applicable - standard TSSOP8 with gull-wing leads and pin 1 indicator notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselecting resets internal state except WEL/WIP bits. |
| C | Serial clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q); supports CPOL/CPHA = 0/0 or 1/1 modes. |
| D | Serial data input | Carries instructions, addresses, and write data; MSB-first; sampled on rising edge of C. |
| Q | Serial data output | Provides read data, status register contents, or ID page contents; high-impedance when S is high or HOLD is active. |
| W | Write protect | Hardware lock for SRWD, BP1, BP0 bits; when low and SRWD=1, Status register becomes permanently read-only. |
| HOLD | Hold control | Pauses ongoing SPI transfer without deselecting device; Q goes high-Z, D/C ignored; requires S low to activate. |
| VCC | Supply voltage | 2.5–5.5 V operation; requires local 10–100 nF decoupling capacitor near pins to maintain stability during write cycles. |
| VSS | Ground | Reference for all signals; must be low-impedance return path shared with VCC decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| Identification page (64 bytes) | Separate, lockable memory region for storing device-specific keys or calibration data; permanently read-only after LID command execution. |
| Hardware + software write protection | Combines BP1/BP0 bits (software-configurable block lock) with W+SRWD (hardware freeze of status register), enabling multi-layer security for firmware-critical data. |
| HOLD functionality | Enables dynamic bus arbitration - host can suspend EEPROM access mid-transaction to service higher-priority peripherals without losing context or requiring re-initialization. |
| ECOPACK2® packaging | TSSOP8 meets RoHS, halogen-free, and lead-free requirements; 169 mil width ensures compatibility with standard pick-and-place equipment and IPC-7351 footprints. |
| Power-on reset (POR) circuit | Prevents spurious writes during power ramp-up by blocking instruction acceptance until VCC crosses defined threshold, independent of microcontroller reset timing. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers subject to frequent firmware updates and field recalibration. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via SPI during boot and runtime; holds user-modifiable settings immune to power loss. Use Value: Enables zero-downtime parameter updates without EEPROM erase cycles; 64-byte page writes align with Modbus RTU packet boundaries for deterministic update latency. |
Use Scenario: Preserving sensor offset/gain coefficients and regulatory compliance logs in portable diagnostic equipment certified to IEC 62304. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for FDA-required calibration history; ID page locked post-manufacturing to prevent unauthorized modification. Use Value: Meets 21 CFR Part 11 audit trail requirements via hardware-enforced write lock; >200-year retention ensures data validity over full product lifecycle. |
| Automotive Body Control Module (BCM) Settings | Smart Meter Firmware Parameter Backup |
|
Use Scenario: Saving seat/mirror position presets, lighting profiles, and CAN node configuration in automotive BCMs operating across extended temperature ranges. IC Role / Device Role / Timing Role: SPI-connected configuration vault; withstands –40 °C to +85 °C ambient and 5.5 V battery transients without data corruption. Use Value: Eliminates need for external voltage supervisors; built-in POR and VCC monitoring ensure reliable initialization during cold cranking events. |
Use Scenario: Backing up tariff schedules, metering constants, and cryptographic keys in utility smart meters deployed in unattended outdoor enclosures. IC Role / Device Role / Timing Role: Field-upgradeable parameter store accessed during OTA firmware updates; protected against accidental overwrite via BP1/BP0 software locks. Use Value: Supports DLMS/COSEM compliance with secure, authenticated parameter writes; 4M-cycle endurance accommodates daily rate changes over 10+ years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25128B-SSHL-T | 128 Kbit SPI EEPROM, 1.8–5.5 V supply, 20 MHz max clock, but lacks Identification page and hardware SRWD+W lock mechanism. | No dedicated lockable ID page; relies solely on software BP bits for protection - insufficient for regulatory-critical calibration storage. | Select when cost sensitivity outweighs need for hardware-enforced write lock; verify external supervision for status register writes. |
| BR24G128FJ-WE2 | 128 Kbit SPI EEPROM, 1.7–5.5 V supply, 10 MHz max clock, includes write-protect pin but no HOLD function or ID page. | Slower clock limits throughput in high-speed boot loaders; absence of HOLD complicates multi-peripheral SPI bus sharing. | Choose for ultra-low-voltage (1.7 V) operation where 10 MHz bandwidth suffices and bus arbitration is handled externally. |
Compared with AT25128B-SSHL-T and BR24G128FJ-WE2, M95128-WMN6TP uniquely combines 20 MHz speed, hardware-frozen status register, and lockable ID page - making it the only option among the three qualified for safety-critical, audit-trail-compliant, and high-throughput embedded storage.
Availability
M95128-WMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostic devices, automotive body control modules, and smart utility meters requiring stable component supply across extended temperature and voltage ranges.
Supply support for M95128-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
M95128-WMN6TP belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, field-programmable nonvolatile storage in harsh environments with stringent data integrity requirements.
FAQ
Does M95128-WMN6TP support SPI Mode 3 (CPOL=1, CPHA=1)?
Yes, M95128-WMN6TP fully supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In both modes, data is latched on the rising edge of C and output on the falling edge. The only difference is idle clock polarity: C remains low in Mode 0 and high in Mode 3 - allowing seamless integration with microcontrollers configured for either standard.
What happens if the HOLD pin is asserted during a Write cycle?
Asserting HOLD during an active Write cycle pauses communication but does not interrupt the internal self-timed write operation. The device continues programming the addressed page in background; Q goes high-impedance, and D/C are ignored. Once HOLD is deasserted and S remains low, the host may resume reading status or issuing new commands - the WIP bit remains set until tW completes.
Can the Identification page be erased after being locked?
No. Once the Lock Identification Page (LID) instruction is executed with W high and SRWD=1, the 64-byte Identification page becomes permanently read-only. Neither WRITE nor WRID commands will modify its contents, and no command can clear the lock. This one-time irreversible action ensures cryptographic keys or calibration data cannot be altered post-deployment.
Is external decoupling required for stable operation?
Yes. A 10–100 nF ceramic capacitor must be placed between VCC and VSS as close as possible to the TSSOP8 package pins. This suppresses transient current spikes during internal write cycles and clock edges, preventing VCC droop that could trigger premature POR reset or data corruption - especially critical at 20 MHz operation and under load switching conditions.
M95128-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 128Kbit
- Memory Organization:
- 16K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95128-WMN6TP FAQ
1.How can I place an order for M95128-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95128-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95128-WMN6TP reliable?
The price and inventory of M95128-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95128-WMN6TP is usually 5 days.
3.What payment methods are accepted for M95128-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95128-WMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95128-WMN6TP?
M95128-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95128-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95128-WMN6TP?
For technical support, including M95128-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95128-WMN6TP requirements.
6.How does Aetrix verify that M95128-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M95128-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95128-WMN6TP meets industry standards.
7.What is the process for return or replacement of M95128-WMN6TP?
All M95128-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95128-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95128-WMN6TP part is unused and in its original packaging.
Return procedure for M95128-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95128-WMN6TP Tags
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M24C02-WMN6TP
STMicroelectronics
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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24LC01BT-I/OT
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M24C02-FMC6TG
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AT24CS02-SSHM-T
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93LC46BT-I/OT
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