STMicroelectronics M95160-DRDW3TP/K

Overview

M95160-DRDW3TP/K from STMicroelectronics is an AEC-Q100 Grade 0 automotive serial SPI EEPROM with 16-Kbit (2-Kbyte) capacity, 32-byte page size, and extended temperature operation up to +145 °C. It features embedded ECC logic for data integrity, a lockable 32-byte identification page, and supports up to 20 MHz clock frequency in CPOL/CPHA-compatible SPI modes. Used in engine control units for calibration storage under high-temperature under-hood conditions.

For engineers reviewing the M95160-DRDW3TP/K datasheet, M95160-DRDW3TP/K pinout, M95160-DRDW3TP/K application, or M95160-DRDW3TP/K equivalent, key selection criteria include AEC-Q100 Grade 0 qualification, write endurance at 145 °C (≥400k cycles), hardware/software write protection granularity, identification page locking capability, and SO8N/TSSOP8/WFDFPN8 package compatibility with automotive PCB layouts.

Technical Context

This device implements a true EEPROM array organized as 64 pages × 32 bytes (2048 × 8 bits), with dedicated ECC circuitry correcting single-bit errors and detecting double-bit errors per page read. The memory includes a separate 32-byte identification page accessible via RDID/WRID instructions and lockable via LID instruction.

It operates in two supported SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1 - both requiring input latching on rising clock edge and output valid on falling edge. The HOLD pin enables communication pause without chip deselection, while W and SRWD bits jointly enforce status register write protection based on external pin state.

Key Specifications

Pinout & Package

Package: SO8N (150 mil width), TSSOP8 (169 mil width), or WFDFPN8 (2 × 3 mm, ECOPACK2-compliant). Pin numbering follows standard 8-pin DIP/SOIC orientation with pin 1 marked by notch or dot.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar automotive SPI EEPROM applications.

Compared with AT25DF041A-SSH-T and BR24G16NUX-10, the M95160-DRDW3TP/K uniquely delivers AEC-Q100 Grade 0 qualification, embedded ECC, 145 °C operation, and a lockable ID page - making it the sole fit for safety-critical, high-temperature automotive control nodes requiring guaranteed data integrity and long-term reliability.

Availability

M95160-DRDW3TP/K is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, electric power steering modules, and body control modules requiring stable component supply across extended automotive lifecycles.

Supply support for M95160-DRDW3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for automotive, industrial, and consumer markets.

The M95160 series belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical data storage in harsh-temperature environments where AEC-Q100 Grade 0 reliability and ECC-enhanced data integrity are mandatory.

FAQ

What is the function of the HOLD pin on M95160-DRDW3TP/K?

The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. Activation requires S low and C low; during HOLD, Q goes high-impedance while D and C are ignored. This allows microcontrollers to temporarily suspend EEPROM access during higher-priority tasks-such as interrupt handling-without losing synchronization or requiring reinitialization.

How does the identification page differ from main memory?

The identification page is a dedicated 32-byte area separate from the main 2-Kbyte array. It contains pre-programmed ST device ID bytes (0x20, 0x00, 0x0B) and space for user-defined parameters. Unlike main memory, it supports WRID and RDID instructions and can be permanently locked in read-only mode using the LID instruction-preventing accidental overwrite of critical calibration or security data.

Can M95160-DRDW3TP/K operate at 1.7 V while maintaining 20 MHz SPI speed?

Yes-full 20 MHz SPI operation is specified down to 1.7 V supply voltage per DS9286 Rev 8, Table 12. At this minimum VCC, timing parameters including tCLQV (clock to Q valid) and tCLQX (clock to Q high-Z) remain within guaranteed limits, enabling high-speed firmware updates even during low-battery conditions like cold cranking in 12 V automotive systems.

What happens if a write command is issued to a block protected by BP1/BP0 bits?

The device ignores the WRITE or WRSR instruction and does not initiate a write cycle. No status flag is set, and the command appears as a no-op-the WIP bit remains 0 and the WEL bit retains its prior state. Protection is enforced at the silicon level before instruction decode completes, ensuring deterministic behavior even under fault conditions such as corrupted SPI streams or unintended MCU writes.