My Inquiry
My Account
STMicroelectronics M95256-RMN6TP
- Part No.:
- M95256-RMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95256-RMN6TP.pdf
- Description:
- IC EEPROM 256KBIT SPI 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,928
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95256-RMN6TP from STMicroelectronics is a 256-Kbit serial SPI EEPROM organized as 32,768 × 8 bits, designed for nonvolatile data storage in microcontroller-based systems requiring byte- or page-level write capability, hardware/software write protection, and operation down to 1.8 V. It supports 20 MHz clock speed, delivers ≤5 ms page/byte write time, and offers 4 million write cycles with >200-year data retention.
For engineers reviewing the M95256-RMN6TP datasheet, M95256-RMN6TP pinout, M95256-RMN6TP application, or M95256-RMN6TP equivalent, key selection criteria include its 1.8–5.5 V supply range, ECOPACK2-compliant TSSOP8 package, Identification page lockability, and dual SPI mode (CPOL/CPHA = 0/0 or 1/1) compatibility with embedded host controllers.
Technical Context
The device implements a synchronous serial interface compliant with SPI bus protocols, using rising-edge sampling on D and falling-edge output on Q. Its internal architecture includes an HV generator for EEPROM programming, ECC-enabled sense amplifiers, and a status register with nonvolatile BP1/BP0 and SRWD bits controlling software/hardware write protection granularity.
It features dual protection layers: configurable block protection (quarter/half/whole array) via Status register bits, and physical Write Protect (W) pin coupling with SRWD to lock BP/SRWD bits permanently. The HOLD pin enables communication pause without chip deselection, preserving internal state during host interrupt handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32 Kbytes), organized as 32768 × 8 bits - directly addressable via 16-bit SPI address field |
| Page size | 64 bytes - defines minimum write granularity and buffer requirement for efficient firmware updates |
| Write time | ≤5 ms per byte or page - enables deterministic timing for real-time logging and configuration save operations |
| Supply voltage | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V logic, 3.3 V MCU I/O, and 5 V legacy systems |
| Operating temperature | −40 °C to +85 °C - qualified for industrial-grade deployment in automotive body control, smart meters, and PLC modules |
| Endurance | 4 million write cycles - ensures ≥10 years of daily 1,000-write operation in data-logging applications |
| Data retention | 200 years at 25 °C - guarantees long-term integrity of calibration data, serial numbers, and security keys |
Pinout & Package
Supplied in ECOPACK2-compliant TSSOP8 (169 mil width) package with 0.65 mm pitch, lead-free and RoHS-compliant. Pin 1 marked by notch or dot; pin numbering follows standard counter-clockwise convention from top view.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip Select | Active-low enable signal; falling edge required after power-up before first instruction; deselects device and places Q in high-Z |
| C | Serial Clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q); supports 20 MHz max frequency |
| D | Serial Data Input | Input for instructions, addresses, and write data; MSB-first protocol; sampled on rising edge of C |
| Q | Serial Data Output | Output for read data and status register contents; driven only when S is low; high-Z when S is high or HOLD is active |
| W | Write Protect | Hardware control input; used with SRWD bit to lock Status register; must be stable during all write operations |
| HOLD | Hold | Pauses ongoing SPI transaction without resetting internal state; requires S low to activate; Q goes high-Z, D/C ignored |
| VCC | Supply Voltage | 1.8–5.5 V power rail; decoupling capacitor (10–100 nF) required near pins to suppress switching noise during write cycles |
| VSS | Ground | Reference for all signals and internal circuitry; must be low-impedance return path for VCC current |
Key Features
| Feature | Design Value |
|---|---|
| Identification page (64 bytes) | Dedicated locked memory region for storing immutable parameters (e.g., calibration coefficients, device UUIDs); programmable and permanently lockable via LID instruction |
| Multi-level write protection | Software-configurable (BP1/BP0 bits) + hardware-enforced (W + SRWD) protection covering quarter/half/entire array - prevents accidental firmware corruption |
| Dual SPI mode support | Operates in CPOL=0,CPHA=0 and CPOL=1,CPHA=1 modes - interoperable with diverse MCU SPI peripherals without clock polarity reconfiguration |
| Power-on reset (POR) circuit | Prevents spurious writes during power ramp-up; holds device in standby until VCC exceeds POR threshold - eliminates need for external reset supervisor |
| Enhanced ESD protection | ≥4 kV HBM - improves robustness in manufacturing handling and end-equipment field environments with electrostatic exposure risk |
Applications
| Industrial Sensor Calibration | Smart Meter Firmware Storage |
|---|---|
|
Use Scenario: Storing factory-calibrated sensor gain/offset values and temperature compensation coefficients in environmental monitoring nodes. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed at boot and during field recalibration; uses Identification page for permanent calibration constants. Use Value: Enables traceable, tamper-resistant calibration data retention across 200+ years - critical for metrology compliance and audit readiness. |
Use Scenario: Holding firmware update images, tariff tables, and cryptographic keys in utility smart meters deployed in harsh outdoor cabinets. IC Role / Device Role / Timing Role: Secure boot loader storage with hardware write protection (W + SRWD) preventing unauthorized firmware modification. Use Value: Meets IEC 62056-61 security requirements via lockable Identification page and 4M-cycle endurance for frequent OTA updates. |
| Automotive Body Control Module | Medical Device Configuration |
|
Use Scenario: Saving user preferences (seat position, mirror angle), fault logs, and adaptive learning parameters in vehicle BCMs. IC Role / Device Role / Timing Role: Low-voltage (1.8 V) compatible EEPROM interfaced directly to 3.3 V MCU SPI; uses HOLD to suspend writes during CAN interrupt servicing. Use Value: Guarantees reliable parameter persistence over −40 °C to +85 °C ambient and 15-year vehicle lifetime without refresh. |
Use Scenario: Storing FDA-mandated device serial numbers, calibration history, and usage counters in portable diagnostic equipment. IC Role / Device Role / Timing Role: Tamper-evident configuration store with locked Identification page; write-protected via BP1/BP0 to prevent clinical data overwrite. Use Value: Supports 21 CFR Part 11 compliance through immutable, auditable parameter storage with >200-year retention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25SF041-SSHD-B | 4-Mbit SPI Flash (not EEPROM); lacks built-in Identification page and hardware W pin coupling to SRWD | Requires external wear-leveling and locking logic for parameter storage; no native 64-byte lockable page | Select only if higher density and execute-in-place (XIP) code storage are primary needs - not drop-in for M95256-RMN6TP's secure parameter use case |
| BR24G256FJ-WE2 | I²C interface (not SPI); 1.7–5.5 V supply; no HOLD pin or Identification page; 1 million write cycles | Requires I²C-capable MCU; incompatible with existing SPI firmware stack; lower endurance limits field recalibration frequency | Choose only for space-constrained designs where I²C bus sharing justifies interface redesign and reduced write endurance trade-off |
Compared with AT25SF041-SSHD-B and BR24G256FJ-WE2, M95256-RMN6TP uniquely combines SPI interface, hardware-coupled write protection, lockable Identification page, and 4M-cycle endurance - making it optimal for secure, long-life parameter storage rather than generic code or bulk data storage.
Availability
M95256-RMN6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, smart meter firmware storage, automotive body control modules, and medical device configuration requiring stable component supply and long-term lifecycle assurance.
Supply support for M95256-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory products for industrial, automotive, and consumer markets.
M95256-RMN6TP belongs to ST's serial EEPROM product line, engineered specifically for robust, low-voltage, secure nonvolatile storage in resource-constrained embedded systems with stringent reliability and longevity requirements.
FAQ
What is the function of the HOLD pin on M95256-RMN6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low while Chip Select (S) is low, Serial Data Output (Q) enters high-impedance, and Serial Data Input (D) and Clock (C) are ignored. This allows the host MCU to service interrupts or perform other tasks while preserving the exact point in the SPI transaction - essential for deterministic real-time systems.
How does the Identification page differ from the main memory array?
The Identification page is a dedicated 64-byte memory region accessible only via RDID/WRID instructions (not standard READ/WRITE). It supports permanent locking via the LID instruction, after which it becomes read-only. Unlike the main array, its contents survive even if Block Protect bits are cleared - making it ideal for storing immutable identifiers, calibration constants, or cryptographic keys that must never be overwritten.
Can M95256-RMN6TP operate reliably at 1.8 V with full 20 MHz SPI speed?
Yes. The M95256-R variant (including MN6TP suffix) is fully specified for 1.8–5.5 V operation, with AC timing parameters validated down to 1.8 V. Its 20 MHz maximum clock rate applies across the entire voltage range, confirmed in DS4712 Rev 22 AC characteristics (Table 13). No derating is required - enabling direct interface with 1.8 V logic families and ultra-low-power MCUs without level-shifting.
What happens if the Write Protect (W) pin is left floating?
The W pin must be actively driven high or low; floating violates the Absolute Maximum Ratings and may cause undefined behavior, including unintended write protection activation or Status register corruption. ST recommends tying W to VCC (for default unprotected mode) or to VSS (for default protected mode) via a pull-up/down resistor. Internal weak pull-ups/downs are not provided - external biasing is mandatory for robust operation.
M95256-RMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95256-RMN6TP FAQ
1.How can I place an order for M95256-RMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95256-RMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95256-RMN6TP reliable?
The price and inventory of M95256-RMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95256-RMN6TP is usually 5 days.
3.What payment methods are accepted for M95256-RMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95256-RMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95256-RMN6TP?
M95256-RMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95256-RMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95256-RMN6TP?
For technical support, including M95256-RMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95256-RMN6TP requirements.
6.How does Aetrix verify that M95256-RMN6TP is sourced from the original manufacturer or authorized distributors?
All M95256-RMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95256-RMN6TP meets industry standards.
7.What is the process for return or replacement of M95256-RMN6TP?
All M95256-RMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95256-RMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95256-RMN6TP part is unused and in its original packaging.
Return procedure for M95256-RMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95256-RMN6TP Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
