STMicroelectronics M95256-WMN6TP
- Part No.:
- M95256-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95256-WMN6TP.pdf
- Description:
- IC EEPROM 256KBIT SPI 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:9,349
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Product details
Overview
M95256-WMN6TP from STMicroelectronics is a 256-Kbit (32 Kbytes) serial SPI EEPROM organized as 32768 × 8 bits, operating from 2.5 V to 5.5 V over –40 °C to +85 °C. It supports 20 MHz clock speed, 64-byte page writes completing in ≤5 ms, and offers quarter/half/whole-array write protection via BP1/BP0 bits in its Status register. Used in industrial control modules for firmware parameter storage with lockable identification page.
For engineers reviewing the M95256-WMN6TP datasheet, M95256-WMN6TP pinout, M95256-WMN6TP application, or M95256-WMN6TP equivalent, key selection criteria include supply voltage range (2.5–5.5 V), SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), hold functionality for bus arbitration, identification page locking, and ECOPACK2-compliant packaging options including TSSOP8 and WLCSP8.
Technical Context
The device implements a standard SPI interface with dedicated HOLD and W signals enabling real-time bus pause and hardware-based memory protection. Its internal architecture includes an HV generator, ECC-enabled sense amplifiers, and a status register with non-volatile BP1/BP0 and SRWD bits controlling software- and hardware-locked write protection zones.
It supports two SPI modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), latching input on rising C edge and outputting data on falling C edge. The Identification page (64 bytes) is accessible only on M95256-Dx variants - M95256-WMN6TP does not support RDID/WRID/LID instructions per DS4712 Rev 22.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 256 Kbit (32 Kbytes), organized as 32768 × 8 bits - directly addressable via 16-bit SPI address field |
| Interface | SPI bus, CPOL/CPHA = 0/0 or 1/1 - compatible with most microcontroller SPI peripherals without mode translation |
| Max clock frequency | 20 MHz - enables 2.5 MB/s theoretical throughput for page reads/writes |
| Write time | ≤5 ms per byte or per 64-byte page - deterministic timing simplifies firmware timeout handling |
| Supply voltage | 2.5 V to 5.5 V - interoperable with 3.3 V and 5 V logic systems without level shifting |
| Data retention | >200 years at +25 °C - ensures long-term reliability in unpowered storage applications |
| Endurance | >4 million write cycles - supports frequent calibration or logging updates in field-deployed devices |
Pinout & Package
Package: TSSOP8 (169 mil width), ECOPACK2-compliant, surface-mount, 8-pin thin shrink small outline package with exposed pad option (not applicable to MN6TP suffix).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselects device and places Q in high-Z |
| C | Serial clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q) |
| D | Serial data input | MSB-first input for instructions, addresses, and write data; sampled on rising C edge |
| Q | Serial data output | MSB-first output for read data and status register; driven only when S is low |
| W | Write protect | Hardware control for SRWD bit: when W = low and SRWD = 1, Status register becomes read-only |
| HOLD | Hold control | Active-low pause signal; suspends ongoing SPI transfer without resetting internal state or clock sequence |
| VCC | Supply voltage | 2.5–5.5 V power rail; requires local 10–100 nF decoupling capacitor near pins |
| VSS | Ground | Reference for all I/O and internal circuitry; must be low-impedance connection |
Key Features
| Feature | Design Value |
|---|---|
| Page write capability | 64-byte pages enable efficient bulk writes with single command and ≤5 ms latency - reduces MCU overhead vs. byte-by-byte writes |
| Flexible write protection | BP1/BP0 bits configure quarter/half/whole array lock; combined with W/SRWD for hardware-enforced Status register freeze |
| Hold function | Enables multi-master SPI arbitration by pausing active transfers without losing address or instruction context |
| Power-on reset (POR) | Prevents spurious writes during power ramp; device remains unresponsive until VCC exceeds POR threshold (~1.5 V) |
| ECOPACK2 packaging | TSSOP8 footprint meets RoHS, halogen-free, and lead-free requirements - qualified for industrial temperature range |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
Use Scenario: Storing user-configurable I/O mapping and scaling parameters in programmable logic controllers that undergo infrequent but critical reconfiguration. IC Role / Device Role / Timing Role: Non-volatile parameter store accessed via SPI during boot or configuration mode; holds settings across power cycles. Use Value: 200-year data retention and >4M write cycles ensure integrity over 10+ year product lifetimes without battery backup. | Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable ultrasound or ECG units requiring traceable, tamper-resistant values. IC Role / Device Role / Timing Role: Secure configuration memory with write-lockable sectors; BP1/BP0 protect calibration region from accidental overwrite during field service. Use Value: Hardware write protection (W + SRWD) prevents unauthorized modification of calibrated values - satisfies IEC 62304 Class B software safety requirements. |
| Automotive Body Control Module (BCM) Settings | Smart Energy Meter Firmware Parameters |
Use Scenario: Saving seat/mirror position presets and lighting profiles in automotive BCMs where EEPROM must survive repeated ignition cycles and thermal stress. IC Role / Device Role / Timing Role: SPI EEPROM interfaced to 32-bit ARM Cortex-M MCU; withstands –40 °C to +85 °C ambient with no derating. Use Value: 2.5–5.5 V operation matches automotive 3.3 V domain; TSSOP8 package supports automated optical inspection and reflow compatibility. | Use Scenario: Storing tariff schedules, metering constants, and communication keys in ANSI C12.22-compliant smart meters deployed in utility grids. IC Role / Device Role / Timing Role: Secure, long-life memory for cryptographic keys and billing parameters; accessed only during firmware update or commissioning. Use Value: ECOPACK2 compliance ensures environmental conformance; >200-year retention eliminates need for periodic data refresh or backup power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25SF041-SSHD-B | 4 Mbit density, quad SPI support, 1.7–2.0 V min VCC, no HOLD pin | Larger capacity suits firmware storage; lacks HOLD for bus arbitration | Select when higher density or quad mode is needed; verify absence of HOLD does not impact system timing |
| MX25L2006EM1I-12G | 2 Mbit NOR flash, 3-byte addressing, no write protection granularity below sector level | Flash architecture requires erase-before-write; no page-level lock or identification page | Choose only for code storage; avoid for frequent parameter updates due to erase latency and wear leveling complexity |
Compared with AT25SF041 and MX25L2006EM1I, M95256-WMN6TP provides deterministic 5 ms writes, fine-grained (quarter-array) protection, and HOLD functionality essential for real-time embedded systems - making it superior for parameter storage where reliability, low-latency updates, and bus controllability are critical.
Availability
M95256-WMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive body control modules, and smart energy meters requiring stable component supply, long-term data retention, and ECOPACK2-compliant packaging.
Supply support for M95256-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory products for industrial, automotive, and consumer markets.
M95256-WMN6TP belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, SPI-based non-volatile storage in space-constrained industrial and automotive applications requiring high endurance and extended data retention.
FAQ
What SPI modes does M95256-WMN6TP support?
M95256-WMN6TP supports only two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C and output on the falling edge. Mode selection is determined by the host controller; no internal mode register or configuration is required. The device does not support CPOL/CPHA = 0/1 or 1/0.
Does M95256-WMN6TP include an Identification page?
No. The Identification page (64 bytes, accessible via RDID/WRID/LID instructions) is exclusive to M95256-Dx variants (e.g., M95256-DF). M95256-WMN6TP is a -W variant and implements only the standard 32 Kbyte memory array and Status register; RDID and related instructions are invalid and ignored.
How is write protection enforced - by software, hardware, or both?
Write protection uses both: software control via BP1/BP0 bits in the Status register configures protected memory zones (quarter/half/whole array), while hardware enforcement occurs when SRWD = 1 and W pin is driven low - freezing BP1/BP0 and SRWD themselves against further writes. This dual-layer scheme prevents accidental or malicious alteration of protection settings.
Can M95256-WMN6TP operate at 1.8 V?
No. M95256-WMN6TP is the -W version, specified for 2.5 V to 5.5 V operation. For 1.8 V minimum supply, the -R variant (e.g., M95256-RMN6TP) must be used. Attempting to power the -W part below 2.5 V may result in undefined behavior, failed writes, or corrupted data due to insufficient internal charge pump voltage.
M95256-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95256-WMN6TP FAQ
1.How can I place an order for M95256-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95256-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95256-WMN6TP reliable?
The price and inventory of M95256-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95256-WMN6TP is usually 5 days.
3.What payment methods are accepted for M95256-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95256-WMN6TP transactions.
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4.How is shipping managed for M95256-WMN6TP?
M95256-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95256-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95256-WMN6TP?
For technical support, including M95256-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95256-WMN6TP requirements.
6.How does Aetrix verify that M95256-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M95256-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95256-WMN6TP meets industry standards.
7.What is the process for return or replacement of M95256-WMN6TP?
All M95256-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95256-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95256-WMN6TP part is unused and in its original packaging.
Return procedure for M95256-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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