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STMicroelectronics M95320-DRMN3TP/K
- Part No.:
- M95320-DRMN3TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95320-DRMN3TP/K.pdf
- Description:
- IC EEPROM 32KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:12,674
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Product details
Overview
M95320-DRMN3TP/K from STMicroelectronics is an AEC-Q100 Grade 0 automotive EEPROM IC providing 32-Kbit (4-Kbyte) nonvolatile storage via SPI interface, supporting up to 20 MHz clock frequency, 1.7–5.5 V supply, and operation from –40°C to +145°C. It features 128 pages × 32 bytes, embedded ECC logic for data integrity, and a lockable 32-byte identification page used for device ID and application parameters in engine control units and ADAS sensors.
For engineers reviewing the M95320-DRMN3TP/K datasheet, M95320-DRMN3TP/K pinout, M95320-DRMN3TP/K application, or M95320-DRMN3TP/K equivalent, key selection criteria include its extended temperature rating (up to +145°C), hardware/software write protection architecture, page write time ≤4 ms, SO8N/TSSOP8/WFDFPN8 package compatibility, and SPI mode support (CPOL=0/CPHA=0 and CPOL=1/CPHA=1).
Technical Context
The M95320-DRMN3TP/K implements a true EEPROM array with byte-alterable 4096 × 8-bit organization and integrated ECC logic that enhances bit-level reliability during read cycles. Its SPI interface supports dual polarity modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), with data latched on rising C edge and output on falling C edge.
It integrates a status register with WIP (write-in-progress), WEL (write-enable latch), BP0/BP1 (block protect), and SRWD (status register write disable) bits - all nonvolatile except WIP and WEL. Protection is enforced through combined hardware (W pin) and software (SRWD + BP bits) control, enabling quarter-block, half-block, or full-array write lock.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 32-Kbit (4-Kbyte), organized as 128 pages × 32 bytes - enables efficient firmware parameter storage with page-aligned updates. |
| SPI clock max | 20 MHz - supports high-throughput configuration loading in real-time automotive control loops. |
| Operating temp | –40°C to +145°C (Grade 0) - qualified for under-hood ECU and transmission control modules without derating. |
| Write cycle endurance | ≥400,000 cycles at 145°C - ensures long-term reliability in high-temperature powertrain applications. |
| Data retention | ≥50 years at 125°C - guarantees calibration data integrity over full vehicle lifetime under thermal stress. |
| Supply voltage | 1.7 V to 5.5 V - interoperable with 3.3 V and 5 V microcontrollers and tolerant of automotive battery transients. |
| Page write time | Typically 3.2 ms (max 4 ms) - enables fast reconfiguration during boot or diagnostics without blocking host CPU. |
Pinout & Package
Package: TSSOP8 (169 mil width), ECOPACK2-compliant, RoHS and REACH compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C | Serial clock input | Synchronizes all SPI transfers; rising edge latches input data (D), falling edge outputs data (Q). |
| D | Serial data input | Receives instruction, address, and write data; MSB-first, sampled on rising C edge. |
| Q | Serial data output | Outputs read data and status register contents; high-impedance when deselected or in HOLD. |
| S | Chip select input | Active-low enable; edge-sensitive startup ensures robust initialization after power-up. |
| HOLD | Communication pause control | Halts ongoing SPI transfer without deselecting device; requires C low to activate/deactivate. |
| W | Hardware write protect | Controls SRWD-based status register locking; low disables WRSR when SRWD = 1. |
| VCC | Power supply | 1.7–5.5 V input; supports direct connection to MCU I/O rails or regulated 3.3 V/5 V domains. |
| VSS | Ground reference | Common return for all signals and internal circuitry; must be low-impedance for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects multi-bit errors in memory reads - improves functional safety compliance for ASIL-B systems. |
| Lockable ID page | 32-byte dedicated area storing ST device ID and user parameters; permanently read-only after LID command - prevents tampering with calibration or security keys. |
| Schmitt trigger inputs | On C, D, S, HOLD, and W pins - rejects <100 ns noise pulses and ensures reliable operation in noisy automotive environments. |
| Quarter-block software protection | BP0/BP1 bits configure write lock for upper 25%, 50%, or 100% of memory - enables secure partitioning of firmware vs. runtime data. |
| Enhanced ESD/latch-up | 4000 V HBM ESD rating and latch-up immunity per AEC-Q100 - eliminates field failures due to handling or system-level transients. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim values, knock sensor learning maps, and emission calibration tables updated during vehicle operation. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed retention across 15-year vehicle life and thermal cycling from –40°C to +145°C. Use Value: Enables closed-loop engine optimization without external backup power or supercapacitors, reducing BOM cost and board space. |
Use Scenario: Holding camera lens calibration offsets, radar beamforming coefficients, and sensor fusion metadata in front-facing ADAS modules. IC Role / Device Role / Timing Role: Secure, ECC-protected configuration memory accessed during boot and periodic self-test sequences. Use Value: Prevents corruption of safety-critical alignment data under EMI-rich conditions near motors and inverters. |
| Electric Power Steering (EPS) | Transmission Control Module (TCM) |
|
Use Scenario: Recording torque sensor zero-point drift compensation and motor position offset corrections during service intervals. IC Role / Device Role / Timing Role: High-reliability EEPROM interfaced directly to EPS MCU SPI peripheral with CPOL=0/CPHA=0 timing. Use Value: Eliminates need for external voltage supervisors or watchdog timers during write operations due to built-in WIP flag and tW timeout. |
Use Scenario: Maintaining gear ratio learning history, clutch wear counters, and shift schedule adaptations across ignition cycles. IC Role / Device Role / Timing Role: Temperature-hardened memory with hardware (W pin) + software (BP bits) dual-lock for critical drivetrain parameters. Use Value: Ensures write protection remains active even during brown-out events where MCU firmware may be unstable. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4-Mbit SPI Flash (not EEPROM); no built-in ECC; 100k write cycles at 85°C; no ID page. | Lacks AEC-Q100 Grade 0 qualification; rated only to +85°C; unsuitable for under-hood use. | Select only for non-automotive, cost-sensitive applications where byte-alterability and >100k endurance are not required. |
| BR24G32FJ-3GE2 | I²C interface (not SPI); 32-Kbit EEPROM; AEC-Q100 Grade 2 (–40°C to +105°C); no HOLD pin or ID page. | Lower temperature grade limits use to cabin modules; I²C bus contention risk in high-noise environments. | Prefer only when existing I²C infrastructure exists and thermal requirements are less stringent than Grade 0. |
Compared with AT25DF041A-SSH-T and BR24G32FJ-3GE2, the M95320-DRMN3TP/K uniquely delivers Grade 0 temperature operation, SPI-native ECC-protected byte-alterable storage, and a lockable ID page - making it the only choice for safety-critical, high-temperature automotive control nodes requiring guaranteed data integrity over 15+ years.
Availability
M95320-DRMN3TP/K is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, electric power steering systems, and transmission control modules requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for M95320-DRMN3TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade memory solutions.
The M95320-DRMN3TP/K belongs to ST's automotive EEPROM product line, engineered specifically for mission-critical data storage in powertrain, chassis, and ADAS systems where AEC-Q100 Grade 0 reliability and extended temperature operation are mandatory.
FAQ
Is M95320-DRMN3TP/K pin-compatible with earlier M95320 variants like M95320-WMN6TP?
Yes - M95320-DRMN3TP/K uses the same TSSOP8 footprint and pinout as M95320-WMN6TP and M95320-RMN6TP. All share identical signal mapping (C/D/Q/S/HOLD/W/VCC/VSS), identical AC/DC electrical characteristics, and identical instruction set. The "D" prefix denotes Grade 0 qualification and enhanced reliability screening, not mechanical or logical changes.
Does the identification page support both read and write operations after initial programming?
Yes - the 32-byte identification page is fully writable using WRID until locked via the LID instruction. Once LID executes successfully, the entire page becomes read-only and cannot be rewritten or unlocked. The ST device ID (bytes 0–2) is factory-programmed and immutable; subsequent bytes are user-writable before locking.
How does the HOLD function interact with an ongoing write cycle?
HOLD has no effect on an active write cycle (tW). If HOLD is asserted during a write, the device continues internal erase/program operations uninterrupted. Q goes high-impedance, but the write completes normally. HOLD only pauses read/write command sequences - it does not abort or suspend tW, which is self-timed and hardware-controlled.
What SPI modes are supported, and how do they affect MCU peripheral configuration?
M95320-DRMN3TP/K supports only CPOL=0/CPHA=0 and CPOL=1/CPHA=1. In both, data is latched on the rising edge of C and shifted out on the falling edge. MCU SPI peripherals must be configured accordingly - CPOL=0 means idle clock is low; CPOL=1 means idle clock is high. CPHA=0 means sample on first edge, matching both modes' timing requirements.
M95320-DRMN3TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 32Kbit
- Memory Organization:
- 4K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95320-DRMN3TP/K FAQ
1.How can I place an order for M95320-DRMN3TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95320-DRMN3TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95320-DRMN3TP/K reliable?
The price and inventory of M95320-DRMN3TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95320-DRMN3TP/K is usually 5 days.
3.What payment methods are accepted for M95320-DRMN3TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95320-DRMN3TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95320-DRMN3TP/K?
M95320-DRMN3TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95320-DRMN3TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95320-DRMN3TP/K?
For technical support, including M95320-DRMN3TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95320-DRMN3TP/K requirements.
6.How does Aetrix verify that M95320-DRMN3TP/K is sourced from the original manufacturer or authorized distributors?
All M95320-DRMN3TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95320-DRMN3TP/K meets industry standards.
7.What is the process for return or replacement of M95320-DRMN3TP/K?
All M95320-DRMN3TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95320-DRMN3TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95320-DRMN3TP/K part is unused and in its original packaging.
Return procedure for M95320-DRMN3TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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