STMicroelectronics M95320-WMN6P

Overview

M95320-WMN6P from STMicroelectronics is a 32-Kbit serial SPI bus EEPROM organized as 4096 × 8 bits, operating across 2.5 V to 5.5 V supply and -40°C to +85°C ambient. It supports 20 MHz clock speed, 32-byte page writes within 5 ms, and quarter/half/whole memory array write protection via hardware W pin and status register BP bits. Used in industrial control modules for parameter storage and firmware configuration.

For engineers reviewing the M95320-WMN6P datasheet, M95320-WMN6P pinout, M95320-WMN6P application, or M95320-WMN6P equivalent, key selection criteria include verified 4M write cycle endurance, 200-year data retention, SO8N (150-mil) package compatibility, and SPI mode support (CPOL=0/CPHA=0 and CPOL=1/CPHA=1).

Technical Context

This EEPROM implements a standard SPI interface with four active control signals (C, D, Q, S), plus HOLD and W pins for transaction suspension and hardware-based memory protection. The internal architecture includes an address register, data register, page decoder, and non-volatile status register with BP0/BP1 bits controlling protected block size (1/4, 1/2, or full 4 KB array).

Write operations require explicit WREN instruction followed by WRITE command; status polling via RDSR (WIP bit) confirms completion. The device features built-in power-on reset (POR), automatic standby-to-active transition on S low, and high-impedance Q during HOLD or S high - ensuring clean bus arbitration in multi-device SPI systems.

Key Specifications

Pinout & Package

Package: SO8N (ECOPACK2®), 8-lead plastic small outline, 150 mil body width, RoHS-compliant surface-mount package.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT25320B-SSHL-T and BR24G32FJ-3GE2, M95320-WMN6P delivers superior reliability (4M cycles, 200-year retention), robust 20 MHz timing across full voltage range, and enhanced ESD protection - making it optimal for industrial and safety-aware designs requiring long-term data integrity.

Availability

M95320-WMN6P is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive body control modules, and smart energy meters requiring stable component supply across extended temperature and long product lifecycles.

Supply support for M95320-WMN6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and non-volatile memory solutions for industrial, automotive, and consumer markets.

M95320-WMN6P belongs to ST's M95xxx SPI EEPROM family, engineered for high-reliability embedded systems demanding guaranteed data integrity, wide voltage operation, and seamless integration with resource-constrained MCUs.

FAQ

Is M95320-WMN6P pin-compatible with other M95320 variants like M95320-R or M95320-DF?

Yes - all M95320 variants share identical SO8N pinout, signal definitions, and instruction set. The difference lies in voltage range (M95320-W: 2.5–5.5 V; M95320-R: 1.8–5.5 V; M95320-DF: 1.7–5.5 V) and internal qualification grade. Pin-for-pin replacement is valid if supply voltage remains within the target variant's specified range.

Does M95320-WMN6P support Quad SPI or dual-output read modes?

No - M95320-WMN6P implements standard single-data-line SPI (modes 0 and 3 only). It does not support QSPI, dual-I/O, or quad-I/O protocols. Read and write operations use dedicated D (input) and Q (output) lines exclusively, with no multiplexing or enhanced throughput modes.

How is the Identification Page accessed, and is it present in M95320-WMN6P?

The Identification Page (32 bytes) is exclusive to M95320-D variants (e.g., M95320-DW, M95320-DF), not M95320-W. M95320-WMN6P lacks this feature - its memory map is strictly 4096 × 8 bits without reserved ID space. READ/WRITE instructions targeting address 0xFFE0–0xFFFF will wrap or return undefined data.

What happens if Chip Select (S) is deasserted mid-write?

If S goes high during a WRITE instruction, the internal write cycle continues uninterrupted. The device ignores further commands until completion, then sets WIP=0 in the status register. Host software must poll RDSR to confirm completion before issuing new instructions - premature S deassertion does not abort or corrupt the write.