STMicroelectronics M95512-DRDW6TP
- Part No.:
- M95512-DRDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95512-DRDW6TP.pdf
- Description:
- IC EEPROM 512KBIT SPI 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,550
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95512-DRDW6TP from STMicroelectronics is a 512-Kbit (64-Kbyte) serial SPI bus EEPROM organized as 65536 × 8 bits, operating from 1.7 V to 5.5 V supply with 16 MHz max clock speed. It features 128-byte page write capability (≤5 ms), 4M+ write cycles, 200+ year data retention, and hardware/software write protection including quarter/half/whole array lock and an additional 128-byte Identification page for permanent read-only locking in applications such as firmware parameter storage.
For engineers reviewing the M95512-DRDW6TP datasheet, M95512-DRDW6TP pinout, M95512-DRDW6TP application, or M95512-DRDW6TP equivalent, key selection considerations include its dual-voltage support (1.7–5.5 V), ECOPACK2-compliant WLSCP8 package (1.289 × 1.955 mm), SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), HOLD signal for transaction pausing, and nonvolatile BP1/BP0 bit configuration for flexible memory protection granularity.
Technical Context
The device implements a standard SPI interface with dedicated C (clock), D (data in), Q (data out), S (chip select), W (write protect), and HOLD pins, supporting both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes. All input data is latched on the rising edge of C; output data appears on the falling edge. The internal HV generator enables byte/page programming without external high-voltage sources.
It integrates a status register with WIP (Write In Progress), WEL (Write Enable Latch), BP1/BP0 (block protection), and SRWD (Status Register Write Disable) bits - the latter enabling hardware-locked protection when W is low and SRWD is set. The Identification page (available only on -DF variants like this part) adds secure storage for calibration or security keys that can be permanently locked.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 512 Kbit (65536 × 8 bits); sufficient for firmware metadata, calibration tables, or device configuration in space-constrained embedded systems. |
| Supply voltage range | 1.7 V to 5.5 V; supports direct interfacing with 1.8 V microcontrollers and legacy 3.3 V/5 V systems without level shifters. |
| Max SPI clock frequency | 16 MHz; enables fast parameter updates (e.g., sensor calibration writes) with minimal bus occupancy time. |
| Page write time | ≤5 ms per 128-byte page; allows efficient bulk writes while maintaining deterministic timing for real-time host coordination. |
| Data retention | >200 years at +25 °C; ensures long-term reliability in industrial control, metering, and automotive infotainment modules. |
| Endurance | >4 million write cycles; supports frequent logging or runtime parameter adjustment in IoT edge nodes and programmable logic controllers. |
| Operating temperature | −40 °C to +85 °C; qualified for use in outdoor gateways, factory automation I/O modules, and automotive body electronics. |
Pinout & Package
Package: WLSCP8 (WLCSP, 1.289 × 1.955 mm, ECOPACK2-compliant, bump-side down mounting).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | Primary power rail; requires local 10–100 nF decoupling capacitor for stable operation during write cycles. |
| VSS | Ground reference | System ground return path; must be low-impedance and co-located with VCC decoupling. |
| C | Serial clock input | Timing reference for all SPI transactions; sampled on rising edge for input, drives Q on falling edge. |
| D | Serial data input | Carries instruction opcodes, addresses, and write data; latched on rising edge of C. |
| Q | Serial data output | Transmits read data and status register contents; driven on falling edge of C. |
| S | Chip select input | Active-low device enable; falling edge required after power-up before first instruction; enables standby mode when high. |
| W | Hardware write protect | Controls SRWD-based locking of BP1/BP0 bits; low + SRWD=1 disables Status register writes permanently. |
| HOLD | Communication pause | Halts ongoing SPI transfer without deselecting device; Q goes high-Z, D/C ignored until HOLD returns high. |
Key Features
| Feature | Design Value |
|---|---|
| Identification page (128 bytes) | Dedicated nonvolatile area for storing immutable parameters (e.g., serial numbers, cryptographic keys) that can be permanently locked via LID command. |
| Flexible block protection | BP1/BP0 bits configure software-selectable protection zones (none / upper quarter / upper half / full array), enabling tiered access control in multi-firmware systems. |
| HOLD functionality | Enables deterministic interruption of SPI transfers (e.g., during MCU interrupt servicing) without losing internal state or requiring re-initialization. |
| ECOPACK2 packaging | WLSCP8 footprint reduces board area by >70% vs SO8N; compatible with standard SMT assembly and meets RoHS/REACH environmental compliance requirements. |
| Power-on reset (POR) | Prevents spurious writes during power ramp-up by holding device inactive until VCC exceeds POR threshold, independent of minimum operating voltage. |
Applications
| Smart Energy Metering | Industrial PLC Configuration |
|---|---|
Use Scenario: Storing tariff schedules, calibration coefficients, and tamper logs across power cycles in DIN-rail mounted electricity meters. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with guaranteed 200-year retention and 4M+ write endurance under daily firmware updates. Use Value: Eliminates need for battery-backed SRAM; supports remote recalibration via secure Identification page locking of metrology constants. | Use Scenario: Holding I/O mapping tables, PID tuning parameters, and safety-critical configuration in modular programmable logic controllers. IC Role / Device Role / Timing Role: SPI-configurable EEPROM providing deterministic ≤5 ms page writes during runtime reconfiguration without CPU polling. Use Value: Enables field-upgradable logic programs with hardware-enforced write protection (BP1/BP0) to prevent accidental overwrites of safety settings. |
| Automotive Body Control Module | IoT Edge Sensor Node |
Use Scenario: Retaining seat position memory, mirror angle presets, and lighting profiles across vehicle ignition cycles in BCMs. IC Role / Device Role / Timing Role: AEC-Q100 stress-tested EEPROM interfacing directly with 1.8 V CAN microcontrollers via 16 MHz SPI. Use Value: WLSCP8 package fits tight PCB spaces behind dashboard panels; −40 °C to +85 °C rating ensures reliability in under-hood thermal environments. | Use Scenario: Logging environmental sensor readings (temperature/humidity/pressure) and OTA update metadata in battery-powered wireless nodes. IC Role / Device Role / Timing Role: Low-voltage (1.7 V) capable EEPROM enabling operation down to end-of-battery-life while maintaining 128-byte page efficiency. Use Value: HOLD pin allows MCU to suspend EEPROM writes during BLE transmission bursts, preventing bus contention and data corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF512C-SSH-T | 512 Kbit SPI flash (not EEPROM); lacks built-in Identification page and hardware write protect (W) pin; requires external command sequencing for sector protection. | Requires firmware-level emulation of EEPROM semantics; unsuitable for applications needing atomic 128-byte writes or permanent ID-page locking. | Select only if migrating from flash-based designs and accepting higher software overhead for wear leveling and emulated EEPROM behavior. |
| M95512-DWDW6TP | Same die and pinout; differs only in marking - "D" suffix denotes same -DF variant with identical 1.7–5.5 V range and Identification page functionality. | No functional difference; alternate STMicroelectronics orderable part number for identical specification and qualification. | Direct drop-in replacement; verify distributor stock availability and lead time parity before substitution. |
Compared with AT25DF512C-SSH-T, M95512-DRDW6TP delivers true EEPROM behavior (no erase-before-write, deterministic latency), while M95512-DWDW6TP offers identical electrical and functional performance - making the latter ideal for BOM consolidation where dual part numbers exist for logistics reasons.
Availability
M95512-DRDW6TP is available at Aetrix Electronics and suitable for smart energy metering, industrial PLC configuration, and automotive body control modules requiring stable component supply, long-term data integrity, and compact WLSCP8 packaging.
Supply support for M95512-DRDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and nonvolatile memory solutions for industrial, automotive, and consumer markets.
The M95512 product line delivers high-reliability SPI EEPROMs optimized for embedded systems requiring robust data logging, secure parameter storage, and extended temperature operation - with emphasis on low-power, small-footprint, and AEC-Q100-qualified variants.
FAQ
What is the function of the HOLD pin on M95512-DRDW6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low (with S low), Q enters high-impedance, and D/C are ignored. This allows the host MCU to service interrupts or switch peripherals mid-transaction, resuming exactly where it left off upon deassertion - critical for deterministic real-time systems.
How does the Identification page differ from the main memory array?
The Identification page is a dedicated 128-byte region accessible only via RDID/WRID instructions (not standard READ/WRITE). It supports permanent read-only locking via the LID command, making it ideal for storing immutable values like device serial numbers or cryptographic keys - unlike the main array, which remains fully writable unless protected by BP1/BP0 bits.
Can M95512-DRDW6TP operate reliably at 1.7 V supply?
Yes - the "-DF" suffix confirms 1.7 V minimum VCC operation. At 1.7 V, it maintains full 16 MHz SPI capability, 5 ms page write timing, and −40 °C to +85 °C temperature range. This enables direct integration with ultra-low-power MCUs (e.g., STM32L4/L5) without voltage translation, reducing BOM cost and PCB complexity in battery-operated devices.
What happens if the W pin is held low during power-up?
If W is low at power-up and the SRWD bit was previously set, the device enters Hardware Protected mode immediately after POR - freezing BP1/BP0 and SRWD bits as read-only. No WRSR instruction will succeed until W is raised high and SRWD cleared. This provides fail-safe protection against accidental corruption of critical memory protection settings in mission-critical systems.
M95512-DRDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 512Kbit
- Memory Organization:
- 64K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 16 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95512-DRDW6TP FAQ
1.How can I place an order for M95512-DRDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95512-DRDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95512-DRDW6TP reliable?
The price and inventory of M95512-DRDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95512-DRDW6TP is usually 5 days.
3.What payment methods are accepted for M95512-DRDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95512-DRDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95512-DRDW6TP?
M95512-DRDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95512-DRDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95512-DRDW6TP?
For technical support, including M95512-DRDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95512-DRDW6TP requirements.
6.How does Aetrix verify that M95512-DRDW6TP is sourced from the original manufacturer or authorized distributors?
All M95512-DRDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95512-DRDW6TP meets industry standards.
7.What is the process for return or replacement of M95512-DRDW6TP?
All M95512-DRDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95512-DRDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95512-DRDW6TP part is unused and in its original packaging.
Return procedure for M95512-DRDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95512-DRDW6TP Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
