My Inquiry
My Account
STMicroelectronics M95512-RDW6TP
- Part No.:
- M95512-RDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95512-RDW6TP.pdf
- Description:
- IC EEPROM 512KBIT SPI 8TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:17,644
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95512-RDW6TP from STMicroelectronics is a 512-Kbit (64-Kbyte) serial SPI EEPROM organized as 65536 × 8 bits, operating from 1.8 V to 5.5 V supply voltage over –40 °C to +85 °C. It features 128-byte page write capability with ≤5 ms write time, quarter/half/whole-array hardware write protection via BP1/BP0 bits and W pin, and includes a dedicated 128-byte Identification page for permanent lockable configuration storage. It is used in industrial control modules for storing calibration data, device IDs, and firmware revision metadata.
For engineers reviewing the M95512-RDW6TP datasheet, M95512-RDW6TP pinout, M95512-RDW6TP application, or M95512-RDW6TP equivalent, key selection considerations include its 1.8 V minimum VCC support, ECOPACK2-compliant WLSCP8 (1.289 × 1.955 mm) package, 16 MHz SPI clock compatibility, and Identification page lock functionality - critical for secure parameter storage in space-constrained IoT edge nodes.
Technical Context
The device implements a standard SPI interface with CPOL/CPHA = (0,0) or (1,1), latching input data on the rising edge of C and outputting data on the falling edge. Its internal architecture includes an HV generator and sequencer for EEPROM programming, ECC-enabled sense amplifiers, and a status register with non-volatile BP1/BP0 and SRWD bits controlling block protection granularity and hardware write lock.
It supports dual-mode write protection: software-configurable via Status register (BP1/BP0) and hardware-enforced via W pin combined with SRWD bit - enabling irreversible locking of the Identification page. The HOLD signal allows pausing active SPI transactions without deselecting the device, preserving internal state during host interrupt servicing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 512 Kbit (64 Kbyte), organized as 65536 × 8 bits - sufficient for full device configuration + calibration tables in compact embedded systems. |
| Supply voltage range | 1.8 V to 5.5 V - enables direct interfacing with 1.8 V logic microcontrollers and legacy 3.3 V/5 V systems without level shifters. |
| Write cycle endurance | ≥4 million write cycles - supports frequent field-updatable parameters in telemetry gateways and smart sensors. |
| Data retention | ≥200 years at 85 °C - ensures long-term reliability for unattended infrastructure monitoring equipment. |
| SPI clock frequency | Up to 16 MHz - delivers up to 2 MB/s effective throughput for bulk read/write operations in boot-time configuration loading. |
| Page size | 128 bytes - matches typical MCU cache line sizes and minimizes wasted writes when updating partial records. |
| Identification page | 128-byte dedicated area with LID instruction for permanent read-only lock - used for storing cryptographic keys or factory-programmed unique identifiers. |
Pinout & Package
Package: WLSCP8 (WLCSP, 1.289 × 1.955 mm, 8-bump array, ECOPACK2 compliant). Pin mapping verified per DS4192 Rev 24 Figure 3 and Table 2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | 1.8–5.5 V core supply; requires local 10–100 nF decoupling capacitor for stable write operation. |
| VSS | Ground reference | Return path for all signals and internal charge pump; must be low-impedance connection to avoid timing violations. |
| C | Serial clock input | Edge-triggered SPI clock (CPOL/CPHA = 0,0 or 1,1); rising edge latches D, falling edge outputs Q. |
| D | Serial data input | MSB-first input for instructions, addresses, and write data; sampled on rising edge of C. |
| Q | Serial data output | MSB-first output for read data and status register; driven on falling edge of C; high-Z when deselected or in HOLD. |
| S | Chip select input | Active-low enable; falling edge required after power-up before first command; edge-sensitive reset behavior prevents spurious writes. |
| W | Hardware write protect | Combines with SRWD bit to lock Status register; drives BP1/BP0 and SRWD into read-only mode when W = low and SRWD = 1. |
| HOLD | Communication pause | Active-low suspend signal; preserves internal SPI state during host interrupts; requires S = low to activate. |
Key Features
| Feature | Design Value |
|---|---|
| Identification page with lock | 128-byte dedicated memory region programmable via WRID and permanently lockable via LID instruction - enables secure storage of immutable device credentials. |
| Multi-level write protection | Configurable via Status register (BP1/BP0) for quarter/half/full array lock, plus hardware enforcement via W/SRWD - prevents accidental or malicious overwrite of critical firmware data. |
| Low-voltage operation | 1.8 V minimum VCC enables direct integration with ultra-low-power MCUs (e.g., STM32L4/L5) without external regulators or level translators. |
| High-speed SPI interface | 16 MHz max clock supports sub-100 µs page reads and ≤5 ms page writes - reduces boot-time configuration load latency in real-time systems. |
| ECOPACK2 packaging | WLSCP8 footprint (1.289 × 1.955 mm) provides smallest board area among SO8N/TSSOP8/UFDFPN8 options - ideal for wearables and miniaturized sensor nodes. |
Applications
| Industrial Sensor Calibration | Medical Device Configuration |
|---|---|
|
Use Scenario: Storing temperature/pressure offset coefficients and linearization tables in factory-calibrated environmental sensors. IC Role / Device Role / Timing Role: Non-volatile configuration storage with guaranteed 200-year data retention and 4M write cycles for field recalibration events. Use Value: Eliminates need for external OTP or battery-backed RAM; WLSCP8 package fits within 2.0 × 2.5 mm PCB area constraints of MEMS sensor modules. |
Use Scenario: Holding FDA-mandated device serial numbers, manufacturing dates, and calibration timestamps in portable diagnostic tools. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage using locked Identification page for immutable regulatory metadata. Use Value: LID instruction ensures calibration history cannot be altered post-certification - satisfies IEC 62304 traceability requirements. |
| Smart Meter Firmware Metadata | Automotive Body Control Module |
|
Use Scenario: Recording firmware version, update timestamp, and cryptographic signature hash in utility-grade electricity meters. IC Role / Device Role / Timing Role: High-reliability SPI EEPROM interfaced directly to 1.8 V metering SoC; withstands 10k+ field updates over 15-year service life. Use Value: 1.8 V operation avoids level-shifter BOM cost; 16 MHz SPI enables <50 ms firmware header verification during cold boot. |
Use Scenario: Storing seat position presets, mirror angles, and lighting profiles in automotive door modules. IC Role / Device Role / Timing Role: Automotive-grade (-40 °C to +85 °C) EEPROM with hardware write lock (W + SRWD) preventing accidental overwrites during CAN bus firmware updates. Use Value: Quarter-array protection isolates user profile pages from system configuration pages - enables concurrent OTA updates and user customization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF512C-SSH-T | 512 Kbit SPI flash (not EEPROM); lacks Identification page; no hardware W-pin lock; 100k write cycles. | Requires external wear-leveling firmware; unsuitable for frequent small-write applications like calibration logging. | Select only if cost sensitivity outweighs endurance and secure lock requirements. |
| M95512-DFMN6TP | Same die, but in SO8N (150 mil) package; larger footprint (4.9 × 3.9 mm vs. 1.289 × 1.955 mm); identical electrical specs. | Used where reflow compatibility with legacy through-hole or SOIC footprints is required; not suitable for ultra-compact designs. | Choose for prototyping or legacy board reuse; WLSCP8 preferred for production miniaturization. |
Compared with AT25DF512C-SSH-T, M95512-RDW6TP offers 40× higher endurance and secure lockable ID storage; compared with M95512-DFMN6TP, it saves >90% board area while maintaining identical functional safety and data integrity capabilities.
Availability
M95512-RDW6TP is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device configuration, smart meter firmware metadata, and automotive body control modules requiring stable component supply across multi-year production cycles.
Supply support for M95512-RDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
M95512-RDW6TP belongs to ST's serial EEPROM product line, engineered specifically for secure, low-voltage, high-endurance non-volatile storage in space-constrained embedded systems with stringent data integrity requirements.
FAQ
What is the function of the HOLD pin on M95512-RDW6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When driven low while Chip Select (S) is low, Serial Data Output (Q) goes high-impedance and Serial Clock (C) and Serial Data Input (D) become don't-care. This allows the host MCU to service interrupts or perform other tasks while preserving the exact point in the SPI transaction sequence - critical for deterministic real-time systems.
How does the Identification page differ from the main memory array?
The Identification page is a dedicated 128-byte region accessible only via RDID/WRID instructions (not standard READ/WRITE). It supports the LID instruction to permanently lock its contents in read-only mode by setting the SRWD bit and driving W low. Unlike main memory, this page is designed for factory-programmed immutable data such as cryptographic keys, device serial numbers, or calibration certificates - with hardware-enforced write prevention independent of software BP bits.
Can M95512-RDW6TP operate reliably at 1.8 V during write operations?
Yes. The M95512-R variant (including M95512-RDW6TP) is fully specified for write operations down to 1.8 V, with maximum write times of 5 ms per byte or page across the full –40 °C to +85 °C temperature range. Internal charge pump and voltage regulation ensure consistent programming margin at minimum VCC, validated per DS4192 AC timing table tW (Write Cycle Time) under VCC = 1.8 V conditions.
What package type does M95512-RDW6TP use, and why is it significant?
M95512-RDW6TP uses the WLSCP8 (Wafer-Level Chip-Scale Package) with dimensions 1.289 × 1.955 mm and 8 solder bumps. This is the smallest available package in the M95512 family - 75% smaller than SO8N and 60% smaller than TSSOP8. Its significance lies in enabling ultra-compact designs such as wearable health monitors and miniature IoT sensors where board space is constrained and traditional leaded packages are prohibitive.
M95512-RDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 512Kbit
- Memory Organization:
- 64K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 16 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95512-RDW6TP FAQ
1.How can I place an order for M95512-RDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95512-RDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95512-RDW6TP reliable?
The price and inventory of M95512-RDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95512-RDW6TP is usually 5 days.
3.What payment methods are accepted for M95512-RDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95512-RDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95512-RDW6TP?
M95512-RDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95512-RDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95512-RDW6TP?
For technical support, including M95512-RDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95512-RDW6TP requirements.
6.How does Aetrix verify that M95512-RDW6TP is sourced from the original manufacturer or authorized distributors?
All M95512-RDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95512-RDW6TP meets industry standards.
7.What is the process for return or replacement of M95512-RDW6TP?
All M95512-RDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95512-RDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95512-RDW6TP part is unused and in its original packaging.
Return procedure for M95512-RDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95512-RDW6TP Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
