STMicroelectronics M95640-WDW6TP
- Part No.:
- M95640-WDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95640-WDW6TP.pdf
- Description:
- IC EEPROM 64KBIT SPI 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,394
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95640-WDW6TP from STMicroelectronics is a 64-Kbit serial SPI bus EEPROM organized as 8192 × 8 bits, operating from 2.5 V to 5.5 V supply voltage over –40 °C to +85 °C ambient temperature. It features 32-byte page write capability, 5 ms typical byte/page write time, and includes a lockable 32-byte identification page for secure parameter storage. Used in industrial control modules for firmware revision tracking and calibration data retention.
For engineers reviewing the M95640-WDW6TP datasheet, M95640-WDW6TP pinout, M95640-WDW6TP application, or M95640-WDW6TP equivalent, key selection criteria include its 20 MHz SPI clock support, hardware/software write protection (W pin + BP bits), Schmitt-trigger noise immunity, ECOPACK2-compliant SO8 package, and 200-year data retention - critical for long-lifecycle embedded systems requiring field-updatable nonvolatile storage.
Technical Context
The M95640-WDW6TP implements a standard SPI interface with CPOL=0/CPHA=0 or CPOL=1/CPHA=1 mode compatibility, using dedicated S (chip select), C (clock), D (data in), Q (data out), W (write protect), and HOLD (communication pause) signals. Its internal architecture includes an HV generator, sequencer, ECC-enabled sense amplifiers, and status register with WIP, WEL, BP1/BP0, and SRWD bits.
It supports dual protection layers: software-configurable quarter/half/full memory block locking via BP bits, and hardware-enforced status register write disable when SRWD=1 and W pin is low. The identification page (32 bytes) is accessible only via RDID/WRID instructions and can be permanently locked in read-only mode using LID instruction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 64 Kbit (8 Kbytes), organized as 8192 × 8 bits - sufficient for bootloader metadata, device ID, and calibration coefficients in space-constrained MCU designs. |
| Page size | 32 bytes - enables efficient partial-page updates without erasing full sectors, reducing wear on frequently modified data regions. |
| Write cycle endurance | >4 million cycles - supports high-frequency logging or configuration updates in industrial telemetry nodes. |
| Data retention | >200 years at 25 °C - ensures long-term reliability in infrastructure equipment with 10+ year service life. |
| SPI clock frequency | Up to 20 MHz - allows sub-500 µs read access time, enabling real-time parameter retrieval in motor control feedback loops. |
| Supply voltage range | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V logic domains, eliminating level-shifting in mixed-voltage systems. |
| Operating temperature | –40 °C to +85 °C - qualified for use in outdoor gateways, automotive body controllers, and factory automation PLCs. |
Pinout & Package
Package: SO8 (ECOPACK2), 150 mil width, RoHS-compliant surface-mount package with standard JEDEC MS-012AC footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable signal; falling edge initiates SPI transaction and resets internal state after power-up. |
| C | Serial clock | Timing reference for bit transfer; supports CPOL/CPHA modes (0,0) and (1,1); sampled on rising edge for input, drives output on falling edge. |
| D | Serial data input | Carries instruction opcodes, addresses, and write data; latched on rising edge of C; MSB-first protocol. |
| Q | Serial data output | Provides read data and status register contents; high-impedance when S is high or HOLD is active. |
| W | Write protect | Hardware lock for status register bits (BP1/BP0/SRWD); when low and SRWD=1, disables WRSR instruction permanently. |
| HOLD | Communication hold | Pauses ongoing SPI transfer without deselecting device; Q goes high-Z, D/C become don't-care; resumes on HOLD high. |
| VCC | Supply voltage | 2.5–5.5 V power rail; requires local 10–100 nF decoupling capacitor near pins to suppress switching noise. |
| VSS | Ground | Reference for all I/O and internal circuitry; must be low-impedance connection to system ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable identification page | 32-byte dedicated memory area for secure storage of MAC address, serial number, or cryptographic keys - permanently read-only after LID command execution. |
| Schmitt-trigger inputs | Enhanced noise immunity on S, C, D, HOLD, and W pins - prevents spurious transitions in electrically noisy industrial environments (e.g., motor drives). |
| Software write protection | Configurable via BP1/BP0 bits to protect upper quarter (1800h–1FFFh), upper half (1000h–1FFFh), or full array (0000h–1FFFh) from accidental writes. |
| Hardware write protection | Status register write disable (SRWD) + W pin logic locks BP/SRWD bits - prevents firmware corruption even during brown-out or reset glitches. |
| ECOPACK2 packaging | Halogen-free, lead-free SO8 package compliant with RoHS and REACH - meets environmental requirements for global industrial and medical certifications. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and firmware version stamps in programmable logic controllers deployed in factory automation lines. IC Role / Device Role / Timing Role: Nonvolatile configuration store accessed via SPI during boot and runtime reconfiguration; supports concurrent read while write-in-progress via WIP polling. Use Value: Enables field-upgradable logic programs without external programming hardware; 200-year retention eliminates recalibration intervals across 15-year equipment lifecycle. |
Use Scenario: Holding sensor offset/gain coefficients, patient-specific therapy profiles, and regulatory compliance logs in portable infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure parameter vault with lockable ID page for FDA-required traceability; accessed only by authenticated firmware during self-test sequences. Use Value: Meets IEC 62304 Class B software safety requirements via hardware-enforced write protection and tamper-evident lock status (RDLS instruction). |
| Automotive Body Control Module | Smart Energy Meter Firmware Metadata |
|
Use Scenario: Recording door lock actuation counts, mirror position presets, and lighting configuration preferences in 12 V automotive BCMs. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 3.3 V microcontroller SPI peripheral; operates reliably during cold-crank (2.5 V min) and load-dump transients. Use Value: Eliminates need for external voltage supervisors or charge pumps; Schmitt-trigger inputs reject alternator ripple noise up to 200 mVpp. |
Use Scenario: Storing tariff schedules, meter serial numbers, and firmware checksums in ANSI C12.22-compliant smart electricity meters deployed in utility grids. IC Role / Device Role / Timing Role: Tamper-resistant storage for revenue-critical data; identification page locked post-manufacturing to prevent cloning or firmware rollback attacks. Use Value: Achieves ANSI C12.10 Level 2 physical security via permanent ID page lock and hardware SRWD/W protection - validated in UL 2900-1 testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit density, quad SPI interface, 3.0–3.6 V only, no identification page | Higher capacity for firmware image storage; lacks lockable ID page and wide-voltage operation | Select when >64 Kbit capacity is required and system uses quad-SPI for bandwidth; not suitable for 2.5 V or 5 V systems. |
| BR24G64FJ-WE2 | I²C interface, 64 Kbit, 1.7–5.5 V, no HOLD pin, no ID page | Lower pin count (5-pin TSSOP), simpler routing; no communication pause or secure ID storage capability | Choose for cost-sensitive, space-constrained designs where SPI is unavailable and HOLD/ID features are unnecessary. |
Compared with AT25DF041A-SSH-T and BR24G64FJ-WE2, the M95640-WDW6TP uniquely combines wide-voltage SPI operation, hardware/software write protection, and a lockable identification page - making it optimal for safety-critical, long-lifecycle, and mixed-voltage embedded systems requiring field-verifiable identity and configuration integrity.
Availability
M95640-WDW6TP is available at Aetrix Electronics and suitable for industrial PLCs, medical infusion pumps, automotive body control modules, and smart energy meters requiring stable component supply across multi-year production runs.
Supply support for M95640-WDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M95640 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, long-retention nonvolatile storage in harsh environments - emphasizing reliability, security, and interoperability with mainstream MCU SPI peripherals.
FAQ
What is the function of the HOLD pin on M95640-WDW6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When driven low while chip select (S) is active, Q goes high-impedance and D/C are ignored, allowing the host MCU to service higher-priority interrupts. Communication resumes automatically when HOLD returns high, preserving bit position and instruction context - essential for deterministic real-time systems.
How does the identification page differ from main memory?
The identification page is a dedicated 32-byte memory region accessible only via RDID/WRID instructions, separate from the main 8192-byte array. It supports permanent read-only locking via the LID instruction, and its lock status is readable via RDLS. Unlike main memory, it cannot be erased or overwritten once locked - making it ideal for storing immutable device identifiers, cryptographic keys, or regulatory certification data.
Can M95640-WDW6TP operate at 2.5 V and still achieve 20 MHz SPI speed?
Yes - the M95640-WDW6TP guarantees full 20 MHz SPI clock operation across its entire 2.5 V to 5.5 V supply range, as verified in AC timing specifications (tCLQV, tCLQX, tCLQZ). At 2.5 V, setup/hold times remain within spec due to internal voltage scaling and Schmitt-trigger input hysteresis, enabling reliable high-speed communication in battery-powered or low-voltage industrial systems without performance derating.
What happens if the W pin is left floating during operation?
The W pin must be actively driven high or low; floating violates the absolute maximum ratings and may cause undefined behavior in status register write protection. If W floats near the logic threshold, SRWD enforcement becomes unreliable, potentially allowing unintended WRSR execution or failing to lock BP bits. STMicroelectronics specifies mandatory pull-up or pull-down - typically 10 kΩ to VCC or VSS - to ensure deterministic hardware protection activation.
M95640-WDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95640-WDW6TP FAQ
1.How can I place an order for M95640-WDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95640-WDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95640-WDW6TP reliable?
The price and inventory of M95640-WDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95640-WDW6TP is usually 5 days.
3.What payment methods are accepted for M95640-WDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95640-WDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95640-WDW6TP?
M95640-WDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95640-WDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95640-WDW6TP?
For technical support, including M95640-WDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95640-WDW6TP requirements.
6.How does Aetrix verify that M95640-WDW6TP is sourced from the original manufacturer or authorized distributors?
All M95640-WDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95640-WDW6TP meets industry standards.
7.What is the process for return or replacement of M95640-WDW6TP?
All M95640-WDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95640-WDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95640-WDW6TP part is unused and in its original packaging.
Return procedure for M95640-WDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95640-WDW6TP Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
