My Inquiry
My Account
STMicroelectronics M95640-WMN6TP
- Part No.:
- M95640-WMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95640-WMN6TP.pdf
- Description:
- IC EEPROM 64KBIT SPI 20MHZ 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:19,216
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95640-WMN6TP from STMicroelectronics is a 64-Kbit serial SPI bus EEPROM organized as 8192 × 8 bits, operating from 2.5 V to 5.5 V supply and rated for -40 °C to +85 °C ambient temperature. It features 32-byte page write capability, 5 ms typical byte/page write time, and includes a lockable 32-byte identification page for secure parameter storage in industrial control and automotive subsystems.
For engineers reviewing the M95640-WMN6TP datasheet, M95640-WMN6TP pinout, M95640-WMN6TP application, or M95640-WMN6TP equivalent, key selection criteria include its 20 MHz SPI clock support, hardware/software write protection (W pin + BP1/BP0 bits), Schmitt-trigger noise filtering on all inputs, and ECOPACK2-compliant SO8 package with verified 8-pin TSSOP mapping.
Technical Context
This device implements a standard SPI interface compliant with CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, latching input data on rising C edge and outputting data on falling C edge. Internal logic includes a status register with WIP, WEL, BP1/BP0, and SRWD bits, enabling granular software block protection and hardware-locked status register writes when W is low and SRWD is set.
Memory architecture comprises main array (0000h–1FFFh) plus an optional identification page (accessible only on M95640-DF variant), though M95640-WMN6TP supports full READ/WRITe, RDSR/WRSR, WREN/WRDI, and HOLD functionality. The HV generator and sequencer manage internal write cycles without external timing components, ensuring autonomous 3.4 ms typical write completion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 64 Kbit (8 Kbytes), organized as 8192 × 8 bits - directly addressable via two-byte SPI address field |
| Page size | 32 bytes - maximum data written per WRITE instruction; enables efficient firmware patching and parameter updates |
| Write time | ≤5 ms (typ. 3.4 ms) - self-timed internal write cycle; no external delay required between WRITE commands |
| SPI clock max | 20 MHz - supports high-throughput configuration loading in real-time systems with tight boot timing |
| Supply range | 2.5 V to 5.5 V - interoperable with 3.3 V and 5 V microcontrollers without level-shifting |
| Data retention | >200 years - ensures long-term calibration data integrity in unattended infrastructure equipment |
| Endurance | >4 million write cycles - suitable for logging applications with frequent timestamped event writes |
Pinout & Package
Package: SO8 (ECOPACK2), 150 mil width, surface-mount, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselects Q to high-Z |
| C | Serial clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q) |
| D | Serial data input | MSB-first instruction/address/data input; sampled on rising C edge; requires stable VIH/VIL |
| Q | Serial data output | MSB-first read data output; driven only when S is low; high-Z when S high or HOLD active |
| W | Write protect | Hardware lock for BP1/BP0/SRWD bits; low + SRWD=1 disables WRSR, enforcing permanent status register protection |
| HOLD | Communication pause | Active-low; suspends ongoing SPI transfer without resetting internal state; requires S low to activate |
| VCC | Supply voltage | 2.5–5.5 V; internal POR circuit prevents spurious writes until VCC exceeds threshold (~1.8 V) |
| VSS | Ground | Reference for all I/O and internal logic; decoupling capacitor (10–100 nF) required near pins |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Eliminates false triggering from noisy PCB traces or EMI in industrial motor drives and power supplies |
| Software block protection | BP1/BP0 bits configure 0%, 25%, 50%, or 100% of memory as read-only - configurable per system security policy |
| Hardware status register lock | SRWD bit + W pin combination permanently disables WRSR - prevents runtime corruption of protection settings |
| HOLD function | Pauses SPI transfers mid-sequence without losing address pointer or command state - critical for multi-master arbitration |
| Enhanced ESD/latch-up | 4000 V HBM rating - sustains repeated electrostatic discharge in automated test and assembly environments |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) |
|---|---|
|
Use Scenario: Storing calibrated sensor offsets, I/O mapping tables, and firmware update metadata across power cycles in programmable logic controllers. IC Role / Device Role / Timing Role: Non-volatile configuration register accessed via SPI during boot and runtime reconfiguration. Use Value: 200-year data retention and >4M endurance ensure 10+ year field deployment without recalibration or replacement. |
Use Scenario: Holding door lock actuator profiles, seat position presets, and lighting dimming curves in vehicle body electronics. IC Role / Device Role / Timing Role: Secure parameter store interfaced to MCU over shared SPI bus with HOLD support for priority interrupt handling. Use Value: Hardware write protection (W + SRWD) prevents accidental overwrite during CAN-based diagnostic sessions. |
| Medical Infusion Pump Calibration | Smart Energy Meter Firmware Patching |
|
Use Scenario: Archiving dose calibration coefficients, pump motor timing constants, and regulatory audit logs in Class II medical devices. IC Role / Device Role / Timing Role: Tamper-resistant storage with lockable ID page for cryptographic keys and calibration signatures. Use Value: Lockable 32-byte ID page (via LID instruction) provides immutable storage for FDA-required traceability data. |
Use Scenario: Applying field-upgradable firmware patches and tariff schedule updates in utility-grade electricity meters. IC Role / Device Role / Timing Role: High-reliability code/data repository supporting atomic 32-byte page writes under brown-out conditions. Use Value: 2.5 V minimum VCC allows operation during battery-backed backup mode when main supply dips below 3 V. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25640B-MAU-Y | Same 64 Kbit SPI EEPROM, but 1.7–5.5 V supply and no HOLD pin; uses different status register bit layout | Lacks HOLD functionality - unsuitable for systems requiring SPI bus arbitration or interrupt-driven pause | Select when HOLD is unused and wider VCC range (1.7 V) is needed for ultra-low-power designs |
| BR24G64FJ-WE2 | I²C interface (not SPI); 1.7–5.5 V; built-in error correction; no identification page or hardware W pin | Requires I²C master instead of SPI; no hardware write lock for status register bits | Select when board already uses I²C peripherals and ECC for enhanced reliability is prioritized over SPI compatibility |
Compared with AT25640B-MAU-Y and BR24G64FJ-WE2, M95640-WMN6TP uniquely combines SPI HOLD support, hardware-enforced status register locking (W + SRWD), and a dedicated lockable ID page - making it optimal for safety-critical, multi-interrupt embedded systems where deterministic bus control and secure parameter storage are mandatory.
Availability
M95640-WMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, automotive BCMs, medical infusion pumps, and smart energy meters requiring stable component supply, long-lifecycle assurance, and ECOPACK2-compliant packaging.
Supply support for M95640-WMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
M95640-WMN6TP belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, SPI-based non-volatile storage in harsh environments with stringent data integrity and security requirements.
FAQ
What is the function of the HOLD pin on M95640-WMN6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When driven low while chip select (S) is active, it forces Q to high-impedance and ignores D and C signals, allowing the host MCU to service higher-priority interrupts and resume exactly where transmission left off - essential for real-time deterministic systems.
How does hardware write protection work with the W pin and SRWD bit?
When the SRWD bit in the status register is set to 1 and the W pin is driven low, the device enters hardware-protected mode: BP1, BP0, and SRWD become read-only, and the WRSR instruction is rejected. This prevents runtime corruption of memory protection settings - a critical feature for certified safety applications where configuration lockdown must be physically enforced.
Can the identification page be used on M95640-WMN6TP?
No - the lockable 32-byte identification page (accessed via RDID/WRID/LID instructions) is exclusive to the M95640-DF variant. M95640-WMN6TP is the -W version, which supports only the main 8 Kbyte array (0000h–1FFFh) and lacks identification page functionality per DS6633 Rev 21 Section 1 and Table 3 footnotes.
What SPI modes does M95640-WMN6TP support, and how are they configured?
M95640-WMN6TP supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes only. It does not support CPOL=0/CPHA=1 or CPOL=1/CPHA=0. Configuration is handled entirely by the host MCU's SPI peripheral; the device automatically adapts based on clock polarity and phase timing - input data is always latched on rising C, output data always appears on falling C.
M95640-WMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 20 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95640-WMN6TP FAQ
1.How can I place an order for M95640-WMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95640-WMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95640-WMN6TP reliable?
The price and inventory of M95640-WMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95640-WMN6TP is usually 5 days.
3.What payment methods are accepted for M95640-WMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95640-WMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95640-WMN6TP?
M95640-WMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95640-WMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95640-WMN6TP?
For technical support, including M95640-WMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95640-WMN6TP requirements.
6.How does Aetrix verify that M95640-WMN6TP is sourced from the original manufacturer or authorized distributors?
All M95640-WMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95640-WMN6TP meets industry standards.
7.What is the process for return or replacement of M95640-WMN6TP?
All M95640-WMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95640-WMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95640-WMN6TP part is unused and in its original packaging.
Return procedure for M95640-WMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95640-WMN6TP Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
