STMicroelectronics M95M01-DFMN6TP
- Part No.:
- M95M01-DFMN6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
M95M01-DFMN6TP.pdf
- Description:
- IC EEPROM 1MBIT SPI 16MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:21,684
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
M95M01-DFMN6TP from STMicroelectronics is a 1 Mbit (131,072 × 8) serial SPI EEPROM with an additional 256-byte identification page, operating from 1.7 V to 5.5 V across –40 °C to +85 °C. It supports up to 16 MHz clock frequency, delivers byte/page write within 5 ms, and provides hardware- and software-based write protection for memory blocks and status register.
For engineers reviewing the M95M01-DFMN6TP datasheet, M95M01-DFMN6TP pinout, M95M01-DFMN6TP application, or M95M01-DFMN6TP equivalent, key selection considerations include identification page programmability, BP1/BP0-configurable block protection, HOLD signal support for transaction pausing, and ECOPACK2-compliant SO8 packaging with verified 8-pin SPI interface timing.
Technical Context
The device implements a standard SPI interface with CPOL/CPHA = (0,0) or (1,1), latching input data on rising C edge and outputting data on falling C edge. It features a non-volatile status register with WIP, WEL, BP1/BP0, and SRWD bits enabling configurable memory locking and hardware write disable when W is low and SRWD = 1.
Memory organization includes main array (0x00000–0x1FFFF) and dedicated identification page (0x20000–0x200FF), accessible only via RDID/WRID instructions. Internal ECC and sense amplifiers support >4 million write cycles and >200-year data retention under industrial temperature conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Mbit (131,072 × 8), including 256-byte identification page for secure parameter storage |
| Supply voltage | 1.7 V to 5.5 V - enables direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers without level shifters |
| Max clock frequency | 16 MHz - supports high-throughput firmware updates and configuration writes in time-critical systems |
| Write cycle time | ≤5 ms per byte or 256-byte page - reduces system latency during nonvolatile parameter save operations |
| Endurance & retention | 4 million write cycles / 200-year data retention - validated for industrial control loggers and medical device calibration storage |
| Operating temperature | –40 °C to +85 °C - qualified for automotive body control modules and outdoor IoT sensor nodes |
| ESD protection | Enhanced HBM ESD rating - improves robustness in handling-sensitive manufacturing and field-replacement scenarios |
Pinout & Package
Package: SO8 (ECOPACK2), 150 mil width, surface-mount, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; falling edge required after power-up before first instruction; deselects device and places Q in high-Z |
| C | Serial clock | Input timing reference; data latched on rising edge (D), output shifted on falling edge (Q); supports 16 MHz max |
| D | Serial data input | MSB-first input path for instructions, addresses, and write data; sampled on rising C edge |
| Q | Serial data output | MSB-first output path for read data and status register; driven on falling C edge; high-Z when S high or HOLD active |
| W | Write protect | Hardware lock for SRWD/BP bits; when low and SRWD = 1, disables WRSR and makes status register read-only |
| HOLD | Hold control | Pauses ongoing SPI transaction without resetting internal state; requires S low; Q goes high-Z, D/C ignored |
| VCC | Supply voltage | 1.7–5.5 V power rail; decoupling capacitor (10–100 nF) recommended near pins for stable write operation |
| VSS | Ground | Reference for all I/O and internal logic; must be connected directly to system ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Identification page | 256-byte dedicated area (0x20000–0x200FF) accessible only via RDID/WRID; supports permanent lock via LID instruction |
| Configurable block protection | BP1/BP0 bits define protected zones: none, upper quarter (0x18000–0x1FFFF), upper half (0x10000–0x1FFFF), or full array |
| HOLD functionality | Enables real-time SPI transaction suspension without chip deselection-critical for multi-master bus arbitration |
| Status register security | SRWD + W pin combination enforces hardware-level write disable of BP/SRWD bits, preventing accidental reconfiguration |
| Power-on reset (POR) | Internal POR ensures WEL=0 and WIP=0 at startup; prevents spurious writes during voltage ramp-up |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module |
|---|---|
|
Use Scenario: Storing calibrated sensor offsets, I/O mapping tables, and firmware update flags in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed via SPI during boot and runtime parameter adjustment. Use Value: Identification page stores factory-trimmed values locked permanently; BP bits prevent field overwrite of critical calibration data. |
Use Scenario: Retaining seat position memory, mirror angle settings, and lighting profiles across vehicle ignition cycles. IC Role / Device Role / Timing Role: SPI-connected persistent memory for user preference storage with fast 5 ms page writes during power-down save. Use Value: 1.7 V operation ensures reliable write completion during battery brownout; HOLD supports safe interruption during CAN bus arbitration. |
| Medical Device Calibration Log | Smart Meter Firmware Parameter Bank |
|
Use Scenario: Recording calibration coefficients, usage counters, and diagnostic timestamps in portable infusion pumps and glucose monitors. IC Role / Device Role / Timing Role: Secure, long-life data logger interfaced to ARM Cortex-M MCU via SPI with CRC-checked reads. Use Value: 200-year retention and 4M-cycle endurance meet ISO 13485 requirements; identification page holds regulatory traceability IDs. |
Use Scenario: Storing tariff schedules, metering constants, and cryptographic keys in ANSI C12.22-compliant utility meters. IC Role / Device Role / Timing Role: Tamper-resistant configuration vault with hardware write protection enabled by W/SRWD linkage. Use Value: Block protection isolates key storage region from firmware update routines; ECOPACK2 package meets RoHS/REACH compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit capacity, no identification page, 2.7–3.6 V supply only, lacks HOLD pin | Higher density but narrower voltage range; unsuitable for 1.8 V or 5 V systems requiring hold functionality | Select only if higher memory density is needed and system operates strictly at 3.3 V without transaction pausing needs |
| MX25L4005AM2I-12G | 4 Mbit NOR Flash, no EEPROM endurance or byte-write capability, requires sector erase before rewrite | Not drop-in compatible: lacks true byte-write, no identification page, no hardware write protect pin | Use only for code storage-not for frequent parameter updates; requires full erase/write management in firmware |
Compared with AT25DF041A-SSH-T and MX25L4005AM2I-12G, the M95M01-DFMN6TP uniquely combines 1.7 V operation, HOLD signal, identification page, and hardware-enforced block protection-making it optimal for secure, low-voltage, high-endurance configuration storage.
Availability
M95M01-DFMN6TP is available at Aetrix Electronics and suitable for industrial PLC configuration storage, automotive body control modules, medical device calibration logging, and smart meter firmware parameter banking requiring stable component supply and long-term obsolescence management.
Supply support for M95M01-DFMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and nonvolatile memory for industrial, automotive, and consumer applications.
The M95M01 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-voltage, high-reliability configuration and calibration storage in safety-critical embedded systems.
FAQ
What is the function of the HOLD pin on M95M01-DFMN6TP?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting internal state. When asserted low while chip select (S) is active, Q goes high-impedance and D/C are ignored-enabling safe bus arbitration in multi-master systems. It does not affect internal write cycles already in progress.
How does the identification page differ from main memory?
The 256-byte identification page (address 0x20000–0x200FF) is accessible only via RDID/WRID instructions-not standard READ/WRITE-and can be permanently locked in read-only mode using the LID instruction. Unlike main memory, it is intended for immutable factory data such as calibration IDs or security tokens.
Can M95M01-DFMN6TP operate reliably at 1.7 V during write operations?
Yes-the device is fully specified for byte and page writes across its entire 1.7 V to 5.5 V supply range. The internal charge pump and voltage regulation ensure valid tW (≤5 ms) and data integrity at minimum VCC, provided VCC remains stable and decoupled with ≥10 nF capacitance near the pins.
What happens when both W pin and SRWD bit are asserted?
When SRWD = 1 and W is driven low, the device enters hardware-protected mode: BP1/BP0 and SRWD become read-only, and the WRSR instruction is rejected. This prevents accidental or malicious modification of memory protection settings-even if firmware attempts to rewrite the status register.
M95M01-DFMN6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 16 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
M95M01-DFMN6TP FAQ
1.How can I place an order for M95M01-DFMN6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95M01-DFMN6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95M01-DFMN6TP reliable?
The price and inventory of M95M01-DFMN6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95M01-DFMN6TP is usually 5 days.
3.What payment methods are accepted for M95M01-DFMN6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95M01-DFMN6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95M01-DFMN6TP?
M95M01-DFMN6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95M01-DFMN6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95M01-DFMN6TP?
For technical support, including M95M01-DFMN6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95M01-DFMN6TP requirements.
6.How does Aetrix verify that M95M01-DFMN6TP is sourced from the original manufacturer or authorized distributors?
All M95M01-DFMN6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95M01-DFMN6TP meets industry standards.
7.What is the process for return or replacement of M95M01-DFMN6TP?
All M95M01-DFMN6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95M01-DFMN6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95M01-DFMN6TP part is unused and in its original packaging.
Return procedure for M95M01-DFMN6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
M95M01-DFMN6TP Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
