STMicroelectronics M95M01-DWDW4TP/K
- Part No.:
- M95M01-DWDW4TP/K
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95M01-DWDW4TP/K.pdf
- Description:
- IC EEPROM 1MBIT SPI 16MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M95M01-DWDW4TP/K from STMicroelectronics is an automotive-grade 1-Mbit serial SPI EEPROM with AEC-Q100 Grade 0 qualification, ASIL-B ready compliance, and operation up to +145°C. It features 512 pages × 256 bytes, embedded ECC logic for data integrity, a lockable 256-byte identification page, and supports SPI modes CPOL=0/CPHA=0 and CPOL=1/CPHA=1 at up to 16 MHz - deployed in engine control units for calibration storage and fault log retention.
For engineers reviewing the M95M01-DWDW4TP/K datasheet, M95M01-DWDW4TP/K pinout, M95M01-DWDW4TP/K application, or M95M01-DWDW4TP/K equivalent, key selection criteria include write endurance at high temperature (+145°C), hardware/software write protection granularity, identification page locking capability, and SO8N/TSSOP8/WFDFPN8 package compatibility with automotive PCB layout constraints.
Technical Context
This device implements a byte-alterable 131072 × 8-bit memory array organized into 512 pages, with dedicated ECC logic correcting single-bit errors and detecting double-bit errors during read operations. The status register includes WIP (write-in-progress), WEL (write-enable latch), BP0/BP1 (block protect), and SRWD (status register write disable) bits - all nonvolatile except WIP and WEL.
It supports dual-voltage operation (1.7–5.5 V for CMOSF9V variant; 2.5–5.5 V for CMOSF8H), with Schmitt-trigger inputs on all digital pins for noise immunity. The HOLD pin enables communication pause without chip deselection, and the W pin provides hardware-level freeze of BP/SRWD configuration when driven low with SRWD=1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Mbit (131072 × 8 bits), organized as 512 pages of 256 bytes - enables efficient firmware parameter partitioning and page-aligned updates. |
| Operating temperature | −40°C to +145°C (Range 4, CMOSF8H process) - qualified for under-hood automotive applications including transmission control modules. |
| SPI clock frequency | Up to 16 MHz - supports fast calibration data loading during ECU boot without bottlenecking host MCU throughput. |
| Write cycle time | Byte/page write ≤ 5 ms (typ. 4 ms) - ensures <5 ms interruption window for safety-critical logging during runtime. |
| Endurance | ≥ 400 k write cycles at +145°C - guarantees reliable fault log recording over full vehicle lifetime in high-heat zones. |
| Data retention | 100 years at +25°C - maintains calibration maps and VIN data across vehicle ownership and service life. |
| Supply voltage | 2.5 V to 5.5 V - compatible with 3.3 V and 5 V automotive microcontroller I/O domains without level-shifting. |
Pinout & Package
Package: SO8N (150 mil width), TSSOP8 (169 mil width), or WFDFPN8 (2 × 3 mm, ECOPACK2-compliant). Pinout validated per DS9048 Rev 7 Figure 2 and Table 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C | Serial clock input | Timing reference for SPI data latching (rising edge) and output (falling edge); supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes. |
| D | Serial data input | Receives instruction opcodes (e.g., 06h WREN), addresses, and write data - MSB-first, latched on rising C edge. |
| Q | Serial data output | Drives read data, status register contents, or ID bytes - MSB-first, valid after falling C edge; high-Z when deselected or held. |
| S | Chip select input | Edge- and level-sensitive enable: requires prior high-to-low transition after power-up; deselects device and forces Q to high-Z. |
| W | Write protect input | Hardware freeze control for BP0/BP1/SRWD bits when SRWD=1 and W=low - prevents accidental status register corruption in noisy environments. |
| HOLD | Communication hold input | Pauses ongoing SPI transfer without resetting internal state; requires S=low to activate; releases on HOLD high while C is low. |
| VCC | Power supply | 2.5–5.5 V supply rail; must remain stable during all operations; decoupling required per automotive EMC standards. |
| VSS | Ground reference | Common return for all signals and VCC; must be low-impedance connection to minimize ground bounce in high-speed SPI. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects double-bit errors in real time during reads - eliminates need for external CRC checking in safety-critical calibration storage. |
| Lockable identification page | 256-byte dedicated area storing ST device ID (bytes 0–2) and user parameters; permanently lockable via LID instruction - secures VIN, calibration seed, or cryptographic keys. |
| ASIL-B ready compliance | Meets ISO 26262 requirements for systematic capability and diagnostic coverage in automotive safety mechanisms - enables integration into ASIL-B subsystems without additional qualification burden. |
| Quad-level write protection | Software (BP0/BP1 bits) + hardware (W pin) + status register lock (SRWD) + write-enable latch (WEL) - provides layered defense against unintended writes during ECU reset or EMI events. |
| High-temp endurance | 400 k write cycles guaranteed at +145°C - exceeds typical automotive requirement of 100 k cycles at max junction temperature for mission-critical log storage. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance System (ADAS) Camera Module |
|---|---|
|
Use Scenario: Storing and updating fuel injection timing maps, knock sensor adaptation values, and misfire counters across vehicle lifetime. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with ECC-protected read path and page-atomic write - ensures calibration integrity during ignition cycling and thermal stress. Use Value: 100-year data retention at ambient and ≥400 k cycles at +145°C guarantee map persistence through 15+ year vehicle service life without degradation. |
Use Scenario: Retaining camera lens calibration coefficients, ISP firmware patch offsets, and thermal drift compensation tables in front-facing ADAS cameras. IC Role / Device Role / Timing Role: SPI-accessible, lockable ID page stores factory-calibrated lens distortion parameters; ECC ensures bit-error-free coefficient retrieval during image processing pipeline startup. Use Value: Identification page locking prevents field overwrite of critical optical calibration data, eliminating need for re-certification after software update. |
| Electric Power Steering (EPS) Control Module | Automotive Gateway ECU |
|
Use Scenario: Logging torque sensor fault history, motor phase current anomalies, and steering angle offset corrections during vehicle operation. IC Role / Device Role / Timing Role: High-reliability fault log buffer with HOLD pin support - allows uninterrupted logging during CAN bus arbitration delays or MCU interrupt latency spikes. Use Value: HOLD functionality preserves SPI transaction state during 10–100 µs MCU interrupts, preventing log corruption without requiring atomic write buffering in RAM. |
Use Scenario: Storing network routing tables, CAN FD message translation rules, and secure boot public keys across gateway firmware updates. IC Role / Device Role / Timing Role: Dual-protection write scheme (W pin + SRWD) secures boot keys against glitch-based attacks; 16 MHz SPI enables fast key loading during secure boot verification. Use Value: Hardware-enforced write protection of status register prevents malicious modification of BP bits - maintaining immutable key storage even under voltage/frequency fault injection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | No AEC-Q100 Grade 0 qualification; max temp +85°C; no embedded ECC; 4 Mbit capacity. | Lacks ASIL-B readiness and high-temp endurance - unsuitable for under-hood deployment or safety-critical logging. | Select only for non-automotive industrial control where extended temperature and functional safety are not required. |
| BR24G1M-3SPI | AEC-Q100 Grade 2 (−40°C to +105°C); no HOLD pin; no identification page; 1 Mbit with 128-byte page size. | Insufficient temperature range for transmission/ECU use; lacks lockable ID page for secure calibration storage. | Acceptable for body control modules with lower thermal stress but cannot replace M95M01-DWDW4TP/K in powertrain or ADAS systems. |
Compared with AT25DF041A-SSH-T and BR24G1M-3SPI, the M95M01-DWDW4TP/K uniquely delivers AEC-Q100 Grade 0, +145°C operation, embedded ECC, and a lockable identification page - making it the only option among the three qualified for ASIL-B powertrain calibration storage with guaranteed 100-year data integrity.
Availability
M95M01-DWDW4TP/K is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, electric power steering systems, and automotive gateways requiring stable component supply under AEC-Q100 Grade 0 and ASIL-B conditions.
Supply support for M95M01-DWDW4TP/K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with strong focus on functional safety and reliability.
The M95M01 series belongs to ST's automotive EEPROM product line, designed specifically for high-temperature, safety-critical nonvolatile storage in powertrain, chassis, and ADAS systems - emphasizing AEC-Q100 Grade 0 qualification, ECC robustness, and ASIL-B readiness.
FAQ
What is the maximum operating temperature and qualification grade of the M95M01-DWDW4TP/K?
The M95M01-DWDW4TP/K operates from −40°C to +145°C and is qualified to AEC-Q100 Grade 0, meeting the highest automotive reliability standard for under-hood applications. It follows ASIL-B ready requirements per ISO 26262, with documented failure-in-time (FIT) rates and diagnostic coverage metrics available in ST's safety manual UM2314.
How does the identification page differ from main memory, and can it be locked permanently?
The identification page is a dedicated 256-byte region containing ST's device ID (bytes 0–2) and user-programmable space. It supports RDID/WRID instructions and can be permanently locked in read-only mode using the LID instruction - after locking, no further writes are possible, even with WREN/WRSR, ensuring immutability of calibration or security parameters.
Does this EEPROM support both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 SPI modes?
Yes, the M95M01-DWDW4TP/K supports both SPI modes: CPOL=0/CPHA=0 (clock idle low, sample on rising edge) and CPOL=1/CPHA=1 (clock idle high, sample on falling edge). Input data are latched on the rising edge of C, and output data change after the falling edge - matching standard MCU SPI peripheral configurations without custom timing adjustments.
What protection mechanisms prevent unintended writes during power transients or EMI events?
Four independent protections guard against spurious writes: (1) WEL latch requiring explicit WREN instruction, (2) BP0/BP1 bits defining protected memory blocks, (3) SRWD bit + W pin hardware freeze of status register, and (4) Schmitt-trigger inputs rejecting sub-threshold noise. All are validated per AEC-Q100 stress tests including ESD (4 kV HBM) and electrical fast transient (EFT) immunity.
M95M01-DWDW4TP/K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 16 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 145°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95M01-DWDW4TP/K FAQ
1.How can I place an order for M95M01-DWDW4TP/K through Aetrix?
Please submit a Request for Quotation (RFQ) for M95M01-DWDW4TP/K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95M01-DWDW4TP/K reliable?
The price and inventory of M95M01-DWDW4TP/K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95M01-DWDW4TP/K is usually 5 days.
3.What payment methods are accepted for M95M01-DWDW4TP/K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95M01-DWDW4TP/K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95M01-DWDW4TP/K?
M95M01-DWDW4TP/K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95M01-DWDW4TP/K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95M01-DWDW4TP/K?
For technical support, including M95M01-DWDW4TP/K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95M01-DWDW4TP/K requirements.
6.How does Aetrix verify that M95M01-DWDW4TP/K is sourced from the original manufacturer or authorized distributors?
All M95M01-DWDW4TP/K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95M01-DWDW4TP/K meets industry standards.
7.What is the process for return or replacement of M95M01-DWDW4TP/K?
All M95M01-DWDW4TP/K units undergo pre-shipment inspection (PSI). If there is an issue with M95M01-DWDW4TP/K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95M01-DWDW4TP/K part is unused and in its original packaging.
Return procedure for M95M01-DWDW4TP/K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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