STMicroelectronics M95M01-RMN6P

Overview

M95M01-RMN6P from STMicroelectronics is a 1 Mbit (131,072 × 8) serial SPI EEPROM with 256-byte page size, 1.8–5.5 V supply range, and -40 °C to +85 °C operation. It supports up to 16 MHz clock frequency, delivers ≤5 ms byte/page write time, and includes hardware write protection via W pin and software block protection (BP1/BP0 bits). Used in industrial control modules for nonvolatile parameter storage during firmware updates.

For engineers reviewing the M95M01-RMN6P datasheet, M95M01-RMN6P pinout, M95M01-RMN6P application, or M95M01-RMN6P equivalent, key selection criteria include SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), identification page availability (absent in -R variant), hold functionality for interruptible transfers, and ECOPACK2-compliant SO8 package dimensions.

Technical Context

The M95M01-RMN6P implements a standard SPI interface with dedicated HOLD and W pins for real-time transaction suspension and hardware-level write lockout. Its status register contains non-volatile BP1/BP0 bits controlling quarter/half/whole memory array protection, and SRWD bit enabling hardware-locked status register writes when W is low.

It uses internal ECC and page latches to ensure reliable 4 million write cycles and 200-year data retention. The device enters active power mode only when chip select (S) is low, and features built-in POR reset with automatic WEL/WIP bit initialization at power-up.

Key Specifications

Pinout & Package

Package: SO8 (ECOPACK2), 150 mil width, RoHS-compliant surface-mount housing with exposed pad option not applicable.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Compared with AT25DF041A-SSH-T, M95M01-RMN6P provides broader voltage support and deterministic HOLD functionality; compared with M95M02-RMN6TP, it trades 1 Mbit density for lower unit cost and eliminates ID page overhead where not required.

Availability

M95M01-RMN6P is available at Aetrix Electronics and suitable for industrial PLCs, medical infusion pumps, automotive body control modules, and smart energy meters requiring stable component supply across extended temperature and voltage ranges.

Supply support for M95M01-RMN6P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and memory products for industrial, automotive, and consumer markets.

The M95M01 series belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, high-reliability nonvolatile storage in harsh environments where data integrity and long-term stability are mission-critical.

FAQ

What SPI modes does M95M01-RMN6P support?

M95M01-RMN6P supports only two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C (D input) and output shifts on the falling edge (Q output). It does not support CPOL/CPHA = 0/1 or 1/0 configurations, and misconfigured master peripherals will fail communication.

How is hardware write protection implemented on M95M01-RMN6P?

Hardware write protection requires setting the SRWD bit in the status register via WRSR instruction, then driving the W pin low. Once enabled, the SRWD, BP1, and BP0 bits become read-only and WRSR is rejected. Protection persists until power cycle; no unlock sequence exists, ensuring tamper-resistant configuration lockdown.

Does M95M01-RMN6P include an identification page?

No. The identification page (256 bytes, accessible via RDID/WRID/LID instructions) is exclusive to the M95M01-DF variant. M95M01-RMN6P is the -R version and lacks this feature entirely - its memory map is strictly 131,072 × 8 bits without reserved ID space or associated instructions.

What is the maximum clock frequency during write operations?

The maximum clock frequency remains 16 MHz during all operations including write cycles. However, the device internally gates clock during tW (≤5 ms) to manage internal programming voltage generation; host MCU must maintain clock continuity but ignore Q output and poll WIP bit via RDSR instead of assuming timing-based delays.