STMicroelectronics M95M01-RMN6TP

Overview

M95M01-RMN6TP from STMicroelectronics is a 1 Mbit (131,072 × 8) serial SPI EEPROM with 256-byte page size, 1.8–5.5 V supply range, and -40 °C to +85 °C operation. It supports up to 16 MHz clock frequency, delivers ≤5 ms byte/page write time, and includes hardware write protection via W pin and software block protection (BP1/BP0 bits). Used in industrial control modules for parameter storage and firmware configuration backup.

For engineers reviewing the M95M01-RMN6TP datasheet, M95M01-RMN6TP pinout, M95M01-RMN6TP application, or M95M01-RMN6TP equivalent, key selection considerations include SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), identification page availability (not present in -R variant), hold functionality for bus arbitration, and ECOPACK2-compliant SO8 package dimensions.

Technical Context

This device implements a standard SPI interface with dedicated HOLD and WRITE PROTECT inputs for real-time bus pause and memory region locking. It uses an internal high-voltage generator and sequencer for EEPROM programming, with ECC-enabled data register and page latches supporting reliable 256-byte page writes.

The status register (WIP, WEL, BP1/BP0, SRWD) enables dynamic protection control: BP1/BP0 configure quarter/half/whole array lock, while SRWD + W pin jointly enforce hardware write-disable of nonvolatile status bits. No identification page is included in the M95M01-R variant.

Key Specifications

Pinout & Package

Supplied in SO8 (ECOPACK2) package, 150 mil width, with gull-wing leads and industry-standard pin 1 marking. Pinout validated per DS5137 Rev 16 Figure 2 (top view).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Compared with AT25DF041A-SSH-T and BR24G128FJ-WE2, the M95M01-RMN6TP uniquely combines 1 Mbit SPI density, 1.8–5.5 V operation, HOLD functionality, and hardware/software write protection-making it optimal for industrial and automotive systems requiring robust, interruptible, and voltage-flexible nonvolatile storage.

Availability

M95M01-RMN6TP is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics equipment, smart energy meters, and automotive body control modules requiring stable component supply across extended temperature and voltage ranges.

Supply support for M95M01-RMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and nonvolatile memory solutions for industrial, automotive, and consumer markets.

The M95M01 product line delivers high-reliability serial EEPROMs optimized for mission-critical configuration storage in harsh environments-designed specifically for systems demanding long data retention, high write endurance, and robust SPI interoperability.

FAQ

Does M95M01-RMN6TP support SPI Mode 3 (CPOL=1, CPHA=1)?

Yes, the device supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In both modes, data is latched on the rising edge of C (D input) and output shifts on the falling edge (Q output). The difference lies only in idle clock polarity: C remains high in Mode 3, enabling compatibility with microcontrollers that default to that configuration.

What happens if the HOLD pin is asserted during a write cycle?

Asserting HOLD during an active write cycle pauses communication but does not abort the internal programming operation. The device continues the tW write cycle (≤5 ms) transparently. Once HOLD is deasserted and S remains low, the host may issue a new instruction-however, the WIP bit must be polled to confirm completion before issuing further commands.

Can the write-protect feature be disabled after enabling hardware protection (SRWD=1 and W=low)?

No. When SRWD = 1 and W is driven low, the status register enters hardware-protected mode: BP1, BP0, and SRWD become permanently read-only, and WRSR instructions are rejected. This state persists until power cycle, but cannot be reversed-even with W pulled high-unless SRWD was previously cleared before setting it.

Is the SO8 package of M95M01-RMN6TP compatible with JEDEC MS-012AA footprint?

Yes. The MN package code denotes a standard 150 mil SO8 (8-pin small outline integrated circuit) conforming to JEDEC MO-012AA (also known as MS-012AA), with 1.27 mm lead pitch, 5.0 mm body width, and gull-wing leads. Footprint matches common PCB libraries for SOIC-8 without modification.