STMicroelectronics M95M04-DRCS6TPVF
- Part No.:
- M95M04-DRCS6TPVF
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-UFBGA, WLCSP
- Datasheet:
-
M95M04-DRCS6TPVF.pdf
- Description:
- IC EEPROM 4MBIT SPI 10MHZ 8WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M95M04-DRCS6TPVF from STMicroelectronics is a 4-Mbit serial SPI EEPROM organized as 524,288 × 8 bits, serving as non-volatile program/data storage in microcontroller-based systems. It operates from 1.8 V to 5.5 V, supports up to 10 MHz SPI clock (≥2.5 V), delivers 512-byte page writes in ≤5 ms, and includes a lockable 512-byte identification page for secure parameter storage - used in industrial PLCs, medical sensor calibration modules, and automotive body control units.
For engineers reviewing the M95M04-DRCS6TPVF datasheet, M95M04-DRCS6TPVF pinout, M95M04-DRCS6TPVF application, or M95M04-DRCS6TPVF equivalent, key selection criteria include its dual-voltage SPI timing (5 MHz @ 1.8 V / 10 MHz @ 2.5 V), hardware/software write protection hierarchy (BP1/BP0 + W pin + SRWD), 4-million-cycle endurance, and WLCSP8/SO8N/TSSOP8 package options with ECOPACK2 compliance.
Technical Context
This SPI EEPROM implements a synchronous serial interface compliant with CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes, with data latched on C's rising edge and output on its falling edge. It integrates an internal high-voltage generator and sequencer for byte/page programming, plus ECC-enabled sense amplifiers and page latches for reliable 512-byte page writes.
The device features a dual-layer protection architecture: software-configurable quarter/half/full memory block locking via BP1/BP0 bits in the status register, and hardware-enforced status register write disable when SRWD=1 and W pin is low. Its Schmitt-trigger inputs ensure noise immunity on HOLD, W, and S pins across industrial temperature ranges.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Mbit (524,288 × 8) - supports firmware patch storage or multi-sensor calibration tables in space-constrained designs |
| SPI clock max | 10 MHz at VCC ≥ 2.5 V - enables <100 μs read latency for real-time configuration access |
| Page size | 512 bytes - matches typical MCU flash sector sizes for atomic update operations |
| Write cycle time | ≤5 ms (typ. 3.8 ms) per page - allows full 512-byte writes within tight system-level timing budgets |
| Data retention | 200 years - ensures long-term reliability in unattended infrastructure monitoring equipment |
| Endurance | 4 million write cycles - supports daily firmware updates over 10+ years of field operation |
| Supply range | 1.8 V to 5.5 V - interoperable with both 1.8 V logic domains and legacy 3.3/5 V systems |
| Operating temp | −40 °C to +85 °C - qualified for under-hood automotive and factory-floor industrial use |
Pinout & Package
Available in SO8N (150 mil), TSSOP8 (169 mil), and WLCSP8 (2.809 × 1.863 mm) packages - all ECOPACK2-compliant. Pin functions are identical across variants; WLCSP bump mapping follows JEDEC-standard top-view layout with bumps underneath.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C | Serial clock input | Timing reference for all SPI transactions; data latched on rising edge, Q toggled on falling edge |
| D | Serial data input | Receives instruction opcodes, addresses, and write data; MSB-first, sampled on C's rising edge |
| Q | Serial data output | Drives read data and status register contents; high-impedance when deselected or in HOLD |
| S | Chip select input | Active-low enable; edge-sensitive reset behavior prevents spurious writes during power-up |
| W | Hardware write protect | Locks BP1/BP0/SRWD bits when pulled low and SRWD=1 - provides tamper-resistant configuration lockdown |
| HOLD | Communication pause | Halts ongoing SPI transfer without resetting internal state; requires S=low to activate |
| VCC | Power supply | 1.8–5.5 V analog/digital rail; decoupling capacitor (10–100 nF) required near pins |
| VSS | Ground reference | Common return for all signals; must be low-impedance and tied directly to PCB ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Lockable identification page | 512-byte dedicated area permanently configurable as read-only for secure device serialization or calibration keys |
| Dual write protection | Software (BP1/BP0 bits) + hardware (W pin + SRWD bit) layers prevent accidental or malicious memory corruption |
| Ultra-low standby current | 600 nA typical - extends battery life in always-on IoT endpoints and portable diagnostic tools |
| Noise-immune inputs | Schmitt-trigger receivers on S, W, and HOLD pins reject >1.5 Vpp ripple in electrically noisy industrial environments |
| Robust SPI protocol enforcement | Rejects malformed instructions (non-multiple-of-8 clocks) and requires WREN before any write - eliminates bus-induced corruption |
Applications
| Industrial Sensor Calibration | Automotive Body Control Module |
|---|---|
|
Use Scenario: Storing factory-trimmed offset/gain coefficients for pressure and temperature sensors in programmable logic controllers. IC Role / Device Role / Timing Role: Non-volatile parameter store accessed during boot and runtime recalibration; SPI interface synchronized to MCU clock domain. Use Value: Enables field-updatable calibration without reprogramming MCU flash, preserving firmware integrity and reducing service downtime. |
Use Scenario: Retaining user-configured mirror/window position memory and lighting profiles across vehicle ignition cycles. IC Role / Device Role / Timing Role: Persistent configuration storage interfaced to 8-bit/32-bit automotive MCUs via SPI; withstands cold-cranking voltage dips. Use Value: Supports ASIL-B–compatible fail-safe operation with 200-year data retention and −40 °C startup capability. |
| Medical Diagnostic Equipment | Smart Energy Metering |
|
Use Scenario: Archiving patient-specific calibration constants and regulatory audit logs in portable ultrasound and ECG devices. IC Role / Device Role / Timing Role: Secure, tamper-evident storage with lockable ID page for FDA 21 CFR Part 11 compliance. Use Value: Meets IEC 62304 Class C software requirements via hardware-enforced write protection and 4M write-cycle endurance. |
Use Scenario: Storing tariff schedules, metering history, and cryptographic keys in DIN-rail-mounted smart electricity meters. IC Role / Device Role / Timing Role: High-reliability data logger with 10 MHz SPI burst reads for real-time energy reporting over HPLC/RF mesh networks. Use Value: Guarantees 10+ year field life under thermal cycling (−25 °C to +70 °C ambient) with zero data loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit SPI Flash (not EEPROM); lacks byte-write capability and requires sector erase before rewrite | Not suitable for frequent small-data updates (e.g., sensor logs); better for firmware image storage | Select only if application writes are infrequent and aligned to 4-kB sectors |
| BR24G04FJ-WE2 | I²C interface (not SPI); 1.7–5.5 V supply; 1 MHz max clock; no HOLD pin or identification page | Requires I²C-capable host; incompatible with SPI-bus-dense systems needing HOLD arbitration | Choose only when board layout mandates 2-wire interface and HOLD functionality is unnecessary |
Compared with AT25DF041A-SSH-T and BR24G04FJ-WE2, the M95M04-DRCS6TPVF uniquely supports true byte/page EEPROM semantics - enabling single-byte updates without erase, deterministic 3.8-ms writes, and hardware-locked ID storage - making it optimal for dynamic calibration and secure configuration in resource-constrained embedded systems.
Availability
M95M04-DRCS6TPVF is available at Aetrix Electronics and suitable for industrial sensor calibration, automotive body control modules, medical diagnostic equipment, and smart energy metering requiring stable component supply across extended product lifecycles.
Supply support for M95M04-DRCS6TPVF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The M95M04-DR series belongs to ST's high-reliability serial EEPROM product line, engineered specifically for mission-critical non-volatile storage in harsh environments where data integrity, long-term retention, and robust SPI interoperability are mandatory.
FAQ
What SPI modes does M95M04-DRCS6TPVF support?
The device supports only two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C and output on its falling edge. Mode selection depends on the host controller's idle clock polarity - no other combinations (e.g., CPOL=0/CPHA=1) are compatible per DS12179 Rev 4 Section 4.1.
How is the identification page protected and locked?
The 512-byte identification page is protected via the LID (Lock Identification Page) instruction (opcode 1000 0010). Once executed, the page becomes permanently read-only - subsequent WRID attempts return status register WIP=0 but do not modify memory. Lock status is verified using RDLS (Read ID Lock Status), which returns 0x01 if locked.
Can M95M04-DRCS6TPVF operate reliably at 1.8 V with 10 MHz SPI?
No - at 1.8 V, maximum SPI clock frequency is 5 MHz per DS12179 Rev 4 Section "Clock frequency". Attempting 10 MHz operation below 2.5 V violates AC timing specifications and may cause instruction decode failures or data corruption; the device will not function correctly outside this voltage-dependent limit.
What happens to the status register after a power cycle?
On power-up, the WEL and WIP bits reset to 0, but BP1, BP0, and SRWD retain their last written non-volatile values. The POR circuit ensures the device remains unresponsive until VCC exceeds the threshold (~1.5 V), then initializes into standby mode with S high and WEL=0 - preventing unintended writes during voltage ramp-up.
M95M04-DRCS6TPVF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP (2.81x1.86)
M95M04-DRCS6TPVF FAQ
1.How can I place an order for M95M04-DRCS6TPVF through Aetrix?
Please submit a Request for Quotation (RFQ) for M95M04-DRCS6TPVF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95M04-DRCS6TPVF reliable?
The price and inventory of M95M04-DRCS6TPVF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95M04-DRCS6TPVF is usually 5 days.
3.What payment methods are accepted for M95M04-DRCS6TPVF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95M04-DRCS6TPVF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95M04-DRCS6TPVF?
M95M04-DRCS6TPVF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95M04-DRCS6TPVF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95M04-DRCS6TPVF?
For technical support, including M95M04-DRCS6TPVF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95M04-DRCS6TPVF requirements.
6.How does Aetrix verify that M95M04-DRCS6TPVF is sourced from the original manufacturer or authorized distributors?
All M95M04-DRCS6TPVF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95M04-DRCS6TPVF meets industry standards.
7.What is the process for return or replacement of M95M04-DRCS6TPVF?
All M95M04-DRCS6TPVF units undergo pre-shipment inspection (PSI). If there is an issue with M95M04-DRCS6TPVF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95M04-DRCS6TPVF part is unused and in its original packaging.
Return procedure for M95M04-DRCS6TPVF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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