STMicroelectronics M95M04-DRDW6TP
- Part No.:
- M95M04-DRDW6TP
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95M04-DRDW6TP.pdf
- Description:
- IC EEPROM 4MBIT SPI 10MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:18,032
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Product details
Overview
M95M04-DRDW6TP from STMicroelectronics is a 4-Mbit serial SPI EEPROM organized as 524,288 × 8 bits, serving as non-volatile program/data storage in microcontroller-based systems. It operates from 1.8 V to 5.5 V, supports up to 10 MHz SPI clock (≥2.5 V), features 512-byte page write, includes a lockable 512-byte identification page, and guarantees operation from –40 °C to +85 °C.
For engineers reviewing the M95M04-DRDW6TP datasheet, M95M04-DRDW6TP pinout, M95M04-DRDW6TP application, or M95M04-DRDW6TP equivalent, key selection criteria include supply voltage flexibility (1.8–5.5 V), dual SPI mode support (CPOL/CPHA = 0/0 or 1/1), hardware/software write protection, 4 million write cycles, and WLCSP8/SO8N/TSSOP8 package options.
Technical Context
The device implements a standard SPI interface with dedicated C (clock), D (data in), Q (data out), S (chip select), W (write protect), and HOLD pins. It supports two SPI modes-CPOL=0/CPHA=0 and CPOL=1/CPHA=1-with data latched on rising C edge and output shifted on falling C edge.
Memory architecture includes main array (512 KB) plus a separate 512-byte identification page that can be permanently locked in read-only mode. Internal ECC, Schmitt-trigger inputs, and enhanced ESD/latch-up protection ensure robust operation in noisy industrial environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Mbit (524,288 × 8 bits); sufficient for firmware parameter tables or calibration data in resource-constrained MCU designs. |
| Page size | 512 bytes; enables efficient bulk writes without excessive command overhead per transaction. |
| Write cycle time | ≤5 ms (typ. 3.8 ms) for byte/page; allows rapid field updates without blocking host CPU for extended periods. |
| Endurance | 4 million write cycles; supports frequent logging or configuration changes over product lifetime. |
| Data retention | 200 years at +25 °C; ensures long-term reliability of stored calibration or security keys without refresh. |
| VCC range | 1.8 V to 5.5 V; interoperable with 1.8 V logic, 3.3 V microcontrollers, and legacy 5 V systems. |
| SPI clock max | 10 MHz at VCC ≥ 2.5 V; enables high-throughput programming during production or field upgrades. |
| Standby current | 600 nA typical; critical for battery-powered IoT nodes requiring ultra-low quiescent power. |
Pinout & Package
Available in ECOPACK2-compliant SO8N (150 mil), TSSOP8 (169 mil), and WLCSP8 (2.809 × 1.863 mm) packages. The M95M04-DRDW6TP variant uses the WLCSP8 package.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S | Chip select | Active-low enable; must transition low-to-high at byte boundaries to initiate commands; edge-sensitive for power-up safety. |
| C | Serial clock | Timing reference; rising edge latches input (D), falling edge outputs data (Q); supports CPOL=0/1 modes. |
| D | Serial data input | Carries instruction codes, addresses, and write data; MSB-first; sampled on rising C edge. |
| Q | Serial data output | Outputs status register or memory data; high-impedance when deselected or in HOLD; driven on falling C edge. |
| HOLD | Communication pause | Halts ongoing SPI transfer without deselecting device; requires S low and C low to activate; preserves internal state. |
| W | Hardware write protect | Freezes BP1/BP0 bits when SRWD=1; prevents accidental modification of block protection settings. |
| VCC | Supply voltage | 1.8–5.5 V input; requires local 10–100 nF decoupling; POR circuit prevents spurious writes during ramp-up. |
| VSS | Ground reference | Signal and power return; must be low-impedance path to minimize noise coupling into sensitive I/O lines. |
Key Features
| Feature | Design Value |
|---|---|
| Lockable identification page | 512-byte dedicated area for secure storage of calibration constants or cryptographic keys, permanently read-only after lock command. |
| Software/hardware write protection | BP1/BP0 bits configure quarter/half/full memory lock; W pin + SRWD bit enables irreversible hardware freeze of protection settings. |
| Schmitt-trigger inputs | Enhanced noise immunity on S, C, D, HOLD, and W pins; eliminates false triggering in electrically noisy industrial environments. |
| Ultra-low standby current | 600 nA typical enables multi-year battery life in always-on sensor nodes without compromising memory accessibility. |
| ECC and robustness | Built-in error correction and >4 kV HBM ESD rating ensure reliable operation in automotive body control modules and factory automation PLCs. |
Applications
| Industrial Sensor Node | Automotive Body Control Module |
|---|---|
|
Use Scenario: Storing calibrated sensor offsets and temperature compensation coefficients in wireless environmental monitors. IC Role / Device Role / Timing Role: Non-volatile configuration storage interfaced via SPI to an ARM Cortex-M0+ MCU. Use Value: 200-year data retention and 4 million write cycles ensure field recalibration remains viable across full product lifecycle. |
Use Scenario: Holding door lock actuator timing profiles and seat position memory in 12 V vehicle subsystems. IC Role / Device Role / Timing Role: SPI EEPROM providing persistent parameter storage for LIN-connected ECUs operating at 5 V. Use Value: 1.8–5.5 V supply range and –40 °C to +85 °C rating allow direct integration without level-shifting or thermal derating. |
| Medical Infusion Pump | Smart Energy Meter |
|
Use Scenario: Recording dose history, alarm thresholds, and user preferences in Class II medical devices with battery backup. IC Role / Device Role / Timing Role: Secure, low-power memory storing audit logs and safety-critical configuration data. Use Value: Lockable ID page protects regulatory-mandated calibration data from tampering; 600 nA standby extends battery runtime. |
Use Scenario: Storing tariff schedules, metering firmware patches, and tamper-event logs in ANSI C12.22-compliant meters. IC Role / Device Role / Timing Role: SPI EEPROM used alongside metrology SoC for secure, long-term data archiving. Use Value: Hardware write protection (W + SRWD) prevents unauthorized firmware or billing parameter modification in utility infrastructure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial SPI EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSH-T | 4 Mbit, but uses Quad SPI interface; lacks identification page and hardware write protect (W) pin. | Higher throughput in QSPI-capable hosts; unsuitable where ID page locking or W-pin-based protection is required. | Select only if host supports Quad SPI and hardware-level status register protection is not needed. |
| MX25L4006EM2I-12G | 4 Mbit, SPI NOR flash; no built-in ECC, 100k write cycles, no lockable ID page. | Designed for code storage, not frequent data logging; requires external wear leveling for parameter storage. | Use only for boot code storage; avoid for configuration or calibration data due to endurance and data retention limitations. |
Compared with AT25DF041A-SSH-T and MX25L4006EM2I-12G, the M95M04-DRDW6TP uniquely combines EEPROM endurance, lockable ID page, hardware write protection, and ultra-low standby current-making it optimal for secure, long-life parameter storage rather than code execution or high-speed streaming.
Availability
M95M04-DRDW6TP is available at Aetrix Electronics and suitable for industrial sensor nodes, automotive body control modules, medical infusion pumps, and smart energy meters requiring stable component supply, guaranteed -40 °C to +85 °C operation, and long-term data integrity.
Supply support for M95M04-DRDW6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and non-volatile memory solutions for industrial, automotive, and consumer markets.
The M95M04-DRDW6TP belongs to ST's high-reliability serial EEPROM product line, designed specifically for applications demanding secure, long-life, low-power non-volatile storage in harsh electrical and thermal environments.
FAQ
What SPI modes does the M95M04-DRDW6TP support?
The device supports two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of the serial clock (C) and output on the falling edge. Mode selection depends on host controller configuration; no internal mode switching is required.
How is the identification page protected and locked?
The 512-byte identification page is accessed via RDID/WRID instructions and locked permanently using the LID (Lock Identification Page) command. Once locked, the page becomes read-only and cannot be rewritten-even with WREN enabled-ensuring immutability of calibration or security data.
Can the M95M04-DRDW6TP operate reliably at 1.8 V?
Yes-it is fully specified down to 1.8 V, supporting SPI clock rates up to 5 MHz at this voltage. All DC/AC parameters, including write time (≤5 ms), standby current (600 nA), and noise immunity, are guaranteed across the full 1.8–5.5 V range.
What happens during a power-up sequence?
At power-up, an internal POR circuit holds the device inactive until VCC exceeds the threshold (~1.5 V). Only after VCC stabilizes within 1.8–5.5 V and a falling edge occurs on S does the device accept commands. The status register resets WEL and WIP to 0, preserving BP1/BP0 and SRWD values.
M95M04-DRDW6TP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95M04-DRDW6TP FAQ
1.How can I place an order for M95M04-DRDW6TP through Aetrix?
Please submit a Request for Quotation (RFQ) for M95M04-DRDW6TP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95M04-DRDW6TP reliable?
The price and inventory of M95M04-DRDW6TP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95M04-DRDW6TP is usually 5 days.
3.What payment methods are accepted for M95M04-DRDW6TP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95M04-DRDW6TP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95M04-DRDW6TP?
M95M04-DRDW6TP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95M04-DRDW6TP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95M04-DRDW6TP?
For technical support, including M95M04-DRDW6TP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95M04-DRDW6TP requirements.
6.How does Aetrix verify that M95M04-DRDW6TP is sourced from the original manufacturer or authorized distributors?
All M95M04-DRDW6TP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95M04-DRDW6TP meets industry standards.
7.What is the process for return or replacement of M95M04-DRDW6TP?
All M95M04-DRDW6TP units undergo pre-shipment inspection (PSI). If there is an issue with M95M04-DRDW6TP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95M04-DRDW6TP part is unused and in its original packaging.
Return procedure for M95M04-DRDW6TP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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