STMicroelectronics M95M04-DRMN6TP

Overview

M95M04-DRMN6TP from STMicroelectronics is a 4-Mbit serial SPI bus EEPROM organized as 524,288 × 8 bits, serving as non-volatile program/data storage in microcontroller-based systems. It operates from 1.8 V to 5.5 V, supports up to 10 MHz clock (at ≥2.5 V), delivers 512-byte page writes in ≤5 ms, and guarantees >4 million write cycles with >200-year data retention - deployed in industrial control modules requiring field-upgradable firmware storage.

For engineers reviewing the M95M04-DRMN6TP datasheet, M95M04-DRMN6TP pinout, M95M04-DRMN6TP application, or M95M04-DRMN6TP equivalent, key selection criteria include SPI mode compatibility (CPOL/CPHA = 0/0 or 1/1), hardware/software write protection granularity (quarter-block lockable via BP1/BP0), identification page locking capability, and ultra-low standby current (600 nA) for battery-backed systems.

Technical Context

The device implements a standard SPI interface with dedicated HOLD and W signals for transaction suspension and status register hardware protection. Its internal architecture includes ECC-enabled sense amplifiers, page latches, and an HV generator for reliable byte/page programming across voltage and temperature extremes.

It supports two SPI modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), with data latched on C's rising edge (D) and output on falling edge (Q). The 512-byte identification page is separately lockable to read-only mode, and block protection is configurable via non-volatile BP1/BP0 bits in the status register.

Key Specifications

Pinout & Package

Supplied in ECOPACK2-compliant SO8N (150 mil width) package. Pin functions are validated per DS12179 Rev 4 Figure 2 and Table 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT25DF041A-SSHN-B and BR24G04FJ-WE2, the M95M04-DRMN6TP uniquely combines SPI-native byte/page write, integrated HOLD for deterministic interrupt response, and a lockable identification page - making it optimal for mixed-code-and-configuration embedded systems where update atomicity and security are co-required.

Availability

M95M04-DRMN6TP is available at Aetrix Electronics and suitable for industrial PLC I/O modules, automotive body control units, and medical infusion pumps requiring stable component supply with guaranteed long-term manufacturability.

Supply support for M95M04-DRMN6TP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

This device belongs to ST's serial EEPROM product line, engineered specifically for robust, low-power, SPI-compatible non-volatile storage in space-constrained and mission-critical embedded systems.

FAQ

What SPI modes does the M95M04-DRMN6TP support?

The M95M04-DRMN6TP supports exactly two SPI modes: CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. In both, data is latched on the rising edge of C (D input) and output on the falling edge (Q output). Mode selection is determined by the host controller; no internal mode register or configuration is required.

How is the identification page protected from accidental overwrite?

The 512-byte identification page is protected in two stages: first, software lock via LID instruction sets its contents to read-only; second, hardware lock is enabled by setting SRWD = 1 in the status register and driving the W pin low. Once hardware-locked, the ID page and BP1/BP0/SRWD bits become permanently immutable.

Can the M95M04-DRMN6TP operate reliably at 1.8 V and 10 MHz?

No - maximum clock frequency is 5 MHz at VCC ≥ 1.8 V. The 10 MHz rating applies only when VCC ≥ 2.5 V. At 1.8 V, exceeding 5 MHz violates AC timing specifications and may cause command misreads or incomplete writes, as confirmed in DS12179 Section 9 AC parameters.

What happens to the status register after a power cycle?

After power-up, the WEL and WIP bits reset to 0, but BP1, BP0, and SRWD retain their last-written non-volatile values. The device enters standby mode with S high and requires a falling edge on S before accepting any instruction - ensuring deterministic initialization without spurious writes.