STMicroelectronics M95M04-DWDW4TP/V
- Part No.:
- M95M04-DWDW4TP/V
- Manufacturer:
- STMicroelectronics
- Category:
- Memory
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M95M04-DWDW4TP/V.pdf
- Description:
- IC EEPROM 4MBIT SPI 10MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
M95M04-DWDW4TP/V from STMicroelectronics is an AEC-Q100 Grade 0 automotive serial EEPROM with 4-Mbit (512-Kbyte) capacity, SPI interface up to 10 MHz, and operation from −40°C to +145°C. It features 512-byte page size, embedded ECC logic for data integrity, and a dedicated 512-byte identification page with permanent lock capability - deployed in engine control units for calibration storage and firmware revision tracking.
For engineers reviewing the M95M04-DWDW4TP/V datasheet, M95M04-DWDW4TP/V pinout, M95M04-DWDW4TP/V application, or M95M04-DWDW4TP/V equivalent, key selection criteria include high-temperature endurance (+145°C), hardware/software write protection granularity, identification page locking behavior, and SPI mode compatibility (CPOL=0/CPHA=0 and CPOL=1/CPHA=1).
Technical Context
The device implements a true EEPROM array organized as 1024 × 512-byte pages with built-in ECC logic correcting single-bit errors and detecting double-bit errors. Its SPI interface supports two standard modes (CPOL=0/CPHA=0 and CPOL=1/CPHA=1), with data latched on rising clock edge and output shifted on falling edge.
Write protection is enforced via non-volatile BP1/BP0 bits (defining quarter/half/full memory lock) and SRWD bit coupled with hardware W pin state. The HOLD pin enables communication pause without chip deselection, while the identification page provides factory-programmed ST device ID (0x20, 0x00, 0x13) plus user-configurable locked storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4 Mbit (524,288 × 8 bits), organized as 1024 pages of 512 bytes - enables large calibration map storage with page-aligned writes. |
| SPI Clock Frequency | Up to 10 MHz - supports fast read/write cycles in real-time automotive control loops without bus contention. |
| Operating Temperature | −40°C to +145°C (Grade 0) - qualified for under-hood applications including turbocharger control and exhaust gas recirculation modules. |
| Write Endurance | ≥100 k cycles at +145°C - ensures reliable reprogramming over full vehicle lifetime in high-thermal-stress environments. |
| Data Retention | >10 years at +55°C - guarantees long-term integrity of safety-critical configuration data without refresh. |
| Supply Voltage | 2.9 V to 5.5 V - compatible with 3.3 V and 5 V automotive microcontroller I/O domains without level-shifting. |
| Page Write Time | Typically 2.8 ms (max 4 ms) - enables sub-3ms firmware patching during ECU boot or diagnostic sessions. |
Pinout & Package
Available in ECOPACK2-compliant TSSOP8 (169 mil width) and SO8N (150 mil width) packages. Both use identical 8-pin layout with exposed pad option not specified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| S (Chip Select) | Active-low device enable | Edge- and level-sensitive; must transition high→low to initiate command - prevents spurious writes during power ramp. |
| C (Serial Clock) | Synchronization input | Drives timing for all SPI transfers; supports CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes - matches most MCU SPI peripherals. |
| D (Data Input) | Serial instruction/address/data input | Latches MSB-first on rising C edge - enables robust command framing for WRITE, WRSR, WRID, and LID instructions. |
| Q (Data Output) | Serial data output | Drives MSB-first on falling C edge; enters high-Z when S is high or HOLD is active - avoids bus conflicts in multi-device systems. |
| W (Write Protect) | Status register protection control | Freezes BP1/BP0 block protect settings when SRWD=1 and W=low - enforces immutable memory partitioning in production firmware. |
| HOLD | Communication pause signal | Halts ongoing SPI transfer without resetting internal address counter - allows MCU to service interrupts then resume EEPROM access. |
| VCC | Power supply | 2.9–5.5 V operation with ICC1 standby current ≤1 μA - minimizes quiescent draw in always-on vehicle networks. |
| VSS | Ground reference | Common return for all signals and VCC - requires low-impedance connection to meet AEC-Q100 EMC immunity requirements. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded ECC logic | Corrects single-bit errors and detects double-bit errors across full memory array - eliminates need for external error-handling firmware overhead. |
| Dedicated identification page | 512-byte area with factory-programmed ST ID (0x20, 0x00, 0x13) and user-writable/lockable fields - enables secure device authentication and immutable parameter binding. |
| Hardware + software write protection | SRWD/BP1/BP0 bits + W pin interaction defines four protection states - allows hierarchical lock schemes (e.g., lock calibration but leave diagnostics writable). |
| Schmitt trigger inputs | On S, C, D, HOLD, W pins - rejects noise spikes up to 30% VCC amplitude, meeting ISO 7637-2 pulse 5a/b immunity requirements. |
| High-temp write endurance | 100 k write cycles at +145°C - sustains repeated OTA updates in hot under-hood ECUs without premature wear-out. |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) |
|---|---|
|
Use Scenario: Storing adaptive fuel trim tables and knock sensor learning values that update dynamically during vehicle operation. IC Role / Device Role / Timing Role: Non-volatile parameter retention with byte-alterable writes and ECC-protected reads - critical for closed-loop combustion optimization. Use Value: Enables real-time calibration persistence across ignition cycles without requiring backup battery or capacitor, even at sustained 145°C ambient. |
Use Scenario: Holding camera module lens calibration coefficients and radar beamforming profiles updated during factory alignment and field recalibration. IC Role / Device Role / Timing Role: Secure, lockable storage for safety-critical sensor metadata - accessed only by trusted boot ROM during startup sequence. Use Value: Prevents unauthorized modification of ADAS perception parameters via hardware-enforced write protection and identification page locking. |
| Electric Powertrain Inverter | Body Control Module (BCM) |
|
Use Scenario: Recording IGBT gate driver timing offsets and thermal derating curves adjusted per motor temperature sensor feedback. IC Role / Device Role / Timing Role: High-reliability EEPROM interfaced directly to inverter MCU SPI bus - withstands 145°C junction temperatures near power stages. Use Value: Eliminates need for external thermal shielding or forced air cooling around memory, reducing system BOM and footprint. |
Use Scenario: Storing seat position memory, window auto-up/down thresholds, and lighting scene configurations across vehicle lifetime. IC Role / Device Role / Timing Role: Low-power, long-retention storage accessible during sleep mode via wake-up SPI transaction - supports ultra-low-quiescent-current design. Use Value: Achieves <1 μA standby current while retaining 512 KB of user preferences, extending battery life in parked vehicle scenarios. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-MAHN-T | 4-Mbit SPI NOR Flash (not EEPROM); no byte-write capability; requires sector erase before rewrite. | Lacks true byte-alterability and ECC; unsuitable for dynamic calibration storage with frequent small updates. | Select only if firmware image storage (not runtime parameter logging) is primary use case and erase-cycle tolerance is acceptable. |
| BR24G400FJ-WE2 | I²C interface (not SPI); max +105°C operation; no identification page or HOLD pin. | Cannot replace in SPI-bus-constrained designs; insufficient temperature rating for under-hood placement. | Consider only for cabin-mounted modules where I²C is preferred and thermal stress is below 105°C. |
Compared with AT25DF041A-MAHN-T and BR24G400FJ-WE2, the M95M04-DWDW4TP/V uniquely combines SPI byte-alterability, +145°C endurance, embedded ECC, and lockable identification page - making it the only qualified solution for safety-critical, high-temperature, frequently updated automotive parameter storage.
Availability
M95M04-DWDW4TP/V is available at Aetrix Electronics and suitable for engine control units, ADAS camera modules, electric powertrain inverters, and body control modules requiring stable component supply across extended automotive lifecycles.
Supply support for M95M04-DWDW4TP/V includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management solutions, with broad portfolio certification to AEC-Q100, ISO 26262, and IEC 61508 standards.
The M95M04 series belongs to ST's automotive-grade serial EEPROM product line, engineered specifically for mission-critical data retention in extreme thermal environments - targeting ECU, transmission, and powertrain applications demanding >100k write cycles at 145°C.
FAQ
What is the function of the HOLD pin, and how does it differ from chip deselect?
The HOLD pin pauses ongoing SPI communication without deselecting the device or resetting the internal address counter - allowing the MCU to service higher-priority interrupts and resume exactly where it left off. Unlike chip deselect (S high), which forces Q into high-Z and abandons the transaction, HOLD maintains bus ownership and preserves command context, enabling deterministic timing in real-time automotive software stacks.
How does the identification page locking mechanism work, and what happens after lock activation?
Locking the identification page is performed via the LID instruction (0x82), which permanently sets internal fuses to disable further writes or erases to that 512-byte region. Once locked, RDID and WRID commands still function for read access, but any attempt to write returns status indicating failure. The lock is irreversible and survives power cycles, ensuring factory calibration data or security keys remain tamper-proof throughout vehicle life.
Can the M95M04-DWDW4TP/V operate reliably at 5.5 V supply while maintaining AEC-Q100 Grade 0 qualification?
Yes - the device is fully characterized and qualified from 2.9 V to 5.5 V across the full −40°C to +145°C range. At 5.5 V, all AC timing parameters (including tW = 4 ms max write cycle) and DC specifications (VIH/VIL thresholds, ICC active/standby currents) meet AEC-Q100 Grade 0 limits per DS11938 Rev 5. No derating or reduced functionality applies at maximum VCC.
What SPI modes are supported, and how does the device handle clock polarity ambiguity during idle periods?
The device supports both CPOL=0/CPHA=0 and CPOL=1/CPHA=1 modes. During idle, C remains stable at logic 0 for CPOL=0 and logic 1 for CPOL=1 - eliminating setup-time uncertainty. Data is always latched on the rising edge of C and shifted out on the falling edge, ensuring deterministic sampling regardless of MCU SPI peripheral configuration.
M95M04-DWDW4TP/V Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 10 MHz
- Write Cycle Time - Word, Page:
- 4ms
- Access Time:
- 40 ns
- Voltage - Supply:
- 2.9V ~ 5.5V
- Operating Temperature:
- -40°C ~ 145°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M95M04-DWDW4TP/V FAQ
1.How can I place an order for M95M04-DWDW4TP/V through Aetrix?
Please submit a Request for Quotation (RFQ) for M95M04-DWDW4TP/V on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M95M04-DWDW4TP/V reliable?
The price and inventory of M95M04-DWDW4TP/V are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M95M04-DWDW4TP/V is usually 5 days.
3.What payment methods are accepted for M95M04-DWDW4TP/V?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M95M04-DWDW4TP/V transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M95M04-DWDW4TP/V?
M95M04-DWDW4TP/V orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M95M04-DWDW4TP/V order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M95M04-DWDW4TP/V?
For technical support, including M95M04-DWDW4TP/V datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M95M04-DWDW4TP/V requirements.
6.How does Aetrix verify that M95M04-DWDW4TP/V is sourced from the original manufacturer or authorized distributors?
All M95M04-DWDW4TP/V products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M95M04-DWDW4TP/V meets industry standards.
7.What is the process for return or replacement of M95M04-DWDW4TP/V?
All M95M04-DWDW4TP/V units undergo pre-shipment inspection (PSI). If there is an issue with M95M04-DWDW4TP/V, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M95M04-DWDW4TP/V part is unused and in its original packaging.
Return procedure for M95M04-DWDW4TP/V:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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