STMicroelectronics M95P16-IXMCT/E

Overview

M95P16-IXMCT/E from STMicroelectronics is a 16 Mbit serial SPI page EEPROM with dual/quad output capability, organized as 4096 × 512-byte pages, supporting up to 80 MHz clock frequency, 1.6–3.6 V supply, and industrial temperature range (−40 °C to +85 °C). It integrates ECC for DEC/TED error correction, programmable output drive strength, and SFDP support - deployed in automotive body control modules for nonvolatile parameter storage requiring high write endurance and 100-year data retention.

For engineers reviewing the M95P16-IXMCT/E datasheet, M95P16-IXMCT/E pinout, M95P16-IXMCT/E application, or M95P16-IXMCT/E equivalent, key selection considerations include quad-SPI read throughput (80 MHz w/ dummy byte), page write time (2.0 ms typ), Deep power-down current (0.6 μA), block-level write protection, and WLCSP8/SO8N/UFDFPN8 package compatibility in space-constrained embedded systems.

Technical Context

The M95P16-IXMCT/E implements a dedicated Program/Erase Controller (PEC) that manages self-timed erase-and-program operations across 512-byte pages, ensuring consistent 2.0 ms write performance over full temperature and lifetime. Its memory array is partitioned into 32 blocks (64 KB each) or 512 sectors (4 KB each), with two dedicated 512-byte identification pages - one configurable for UID, the other lockable as read-only for sensitive parameters.

ECC logic operates transparently on every read, delivering double-bit correction and triple-bit detection over 128-bit words, with status flags reported in the Safety register. The device supports CPOL/CPHA = (0,0) and (1,1) SPI modes, and enables quad-output reads by repurposing D-DQ0, W-DQ2, and HOLD-DQ3 as outputs after command address latching - disabling HOLD functionality during quad reads.

Key Specifications

Pinout & Package

Available in UFDFPN8 (2 × 3 mm), SO8N (4.9 × 6.0 mm), and WLCSP8 (1.363 × 1.809 mm) packages - all ECOPACK2 RoHS/halogen-free. Pin functions are identical across packages.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial SPI EEPROM applications.

Compared with AT25DF161-SSH-T and MB85RS1MT-FPN-G-JNE1, the M95P16-IXMCT/E uniquely combines 16 Mbit density, quad-SPI throughput, hardware ECC, and true EEPROM write semantics - eliminating software wear leveling and enabling direct replacement of legacy parallel EEPROMs in safety-certified designs.

Availability

M95P16-IXMCT/E is available at Aetrix Electronics and suitable for automotive body control units, industrial PLC configuration storage, medical infusion pump calibration, and smart meter firmware metadata requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for M95P16-IXMCT/E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management ICs, with R&D centers across Europe, Asia, and the Americas.

The M95P16 belongs to ST's high-reliability serial EEPROM product line, designed specifically for automotive and industrial applications demanding extended temperature operation, robust data integrity, and seamless SPI integration without external logic.

FAQ

Does M95P16-IXMCT/E support true quad-SPI read with command/address phase separation?

Yes. The device implements true quad-SPI read using Fast Read Quad Output (6Bh) command, where D-DQ0, Q-DQ1, W-DQ2, and HOLD-DQ3 all become outputs after the third address byte. Unlike legacy SPI flashes, it does not require separate command/address phases - data begins streaming immediately on the fourth SCK falling edge, achieving 80 MHz effective throughput with one dummy byte.

How is the Unique ID provisioned, and can it be read without factory request?

The first identification page contains factory-programmed device ID and, optionally, a 128-bit UID - but only if requested at order time (via ST part number suffix or special order code). Without explicit UID request, this page holds standard ST manufacturer ID and die revision. The UID is readable via standard Read Identification Page command (4Bh) and cannot be modified post-fabrication.

What happens to ECC status flags after a corrected read, and how are they cleared?

ECC status flags (DEC, TED, DET) in the Safety register are cumulative and sticky: once set by a correction or detection event, they remain asserted until explicitly cleared by writing '1' to their respective bits in the Safety register. They do not auto-clear on subsequent reads, enabling diagnostic firmware to detect and log memory integrity events across power cycles.

Can the second identification page be permanently locked while retaining write access to the main array?

Yes. The second 512-byte identification page can be independently locked as read-only via the LOCK bit in the Configurable register. This lock is irreversible and does not affect write access to the main 4096-page array or the first identification page - allowing secure storage of calibration keys or cryptographic material without compromising firmware update flexibility.