Analog Devices Inc./Maxim Integrated MAX1071ETC

Overview

The MAX1071ETC from Maxim Integrated is a 10-bit, true-differential, serial-output analog-to-digital converter (ADC) operating at up to 1.5 Msps with ±0.5 LSB INL, bipolar input range (–VREF/2 to +VREF/2), and 61 dB SINAD at 525 kHz - designed for high-accuracy signal acquisition in motor control and base-station receiver chains.

For engineers reviewing the MAX1071ETC datasheet, MAX1071ETC pinout, MAX1071ETC application, or MAX1071ETC equivalent, this page delivers verified electrical specs, validated SPI/QSPI/MICROWIRE interface behavior, confirmed TQFN-12 package mapping, and real-world timing constraints including 125 ns acquisition time and 0.667 µs conversion time.

Technical Context

The MAX1071ETC employs a successive-approximation register (SAR) architecture with an internal true-differential track-and-hold (T/H), enabling precise sampling of bipolar differential signals without pipeline delay. Its conversion is initiated by a CNVST falling edge and clocked by SCLK, requiring exactly 16 SCLK cycles per 10-bit result plus 2 sub-bits and 3 leading zeros.

It supports three power states: normal mode (6–8 mA VDD current), partial power-down (1 mA), and full power-down (≤1 µA), all controlled via CNVST/SCLK sequencing. The separate VL supply (1.8 V to VDD) allows direct interfacing with 1.8 V logic while maintaining analog performance.

Key Specifications

Pinout & Package

MAX1071ETC is housed in a 12-pin 3 mm × 3 mm TQFN package with exposed paddle (EP), rated for –40°C to +85°C operation. Pin 1 is AIN–, pin 12 is AIN+, and EP is internally connected to GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit SAR ADC applications.

Compared with ADS8326IDRCT and AD7457BRMZ, the MAX1071ETC uniquely balances 1.5 Msps throughput, bipolar differential input, sub-µA shutdown, and 1.8 V logic compatibility - making it optimal for embedded real-time control where latency, power, and signal range are jointly constrained.

Availability

MAX1071ETC is available at Aetrix Electronics and suitable for motor control feedback, base-station IF digitization, and portable test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for MAX1071ETC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power-management ICs for industrial, communications, and computing applications.

The MAX1070/MAX1071 product line delivers low-power, high-speed SAR ADCs optimized for real-time embedded systems needing deterministic latency, differential noise immunity, and flexible digital interfacing - especially where space, power, and signal integrity are co-constrained.

FAQ

What is the maximum sampling rate supported by the MAX1071ETC, and what conditions apply?

The MAX1071ETC supports a maximum throughput rate of 1.5 Msps under specified conditions: VDD = +2.7 V to +3.6 V, VL ≥ 2.7 V, fSCLK = 24.0 MHz, and VREF = 2.048 V. At VL < 2.7 V, the recommended maximum fSCLK decreases - e.g., 22.5 MHz at VL = 2.1 V - as shown in the Typical Operating Characteristics plot (Figure 1). The minimum conversion time remains fixed at 0.667 µs (16 SCLK cycles).

Does the MAX1071ETC require an external reference, and what are the voltage limits?

Yes, the MAX1071ETC requires an external reference applied to the REF pin. The valid REF input voltage range is +1.0 V to VDD + 50 mV. For optimal performance, Maxim specifies VREF = 2.048 V in electrical characteristics, and recommends bypassing REF with both a 4.7 µF tantalum and a 0.01 µF ceramic capacitor to RGND. DC leakage is ±1 µA, and input capacitance is 20 pF.

How does the MAX1071ETC handle power-down modes, and what are the current savings?

The MAX1071ETC offers two hardware-controlled power-down modes. Partial power-down reduces VDD supply current to 1 mA (typ), while full power-down lowers it to ≤1 µA (max). Entry requires specific CNVST/SCLK timing sequences: partial mode is entered after the 3rd but before the 14th SCLK rising edge; full mode requires repeating that sequence. Recovery from full power-down takes ≤2 ms, and from partial mode ≤16 SCLK cycles.

What digital interfaces is the MAX1071ETC compatible with, and how is data formatted?

The MAX1071ETC supports SPI, QSPI, and MICROWIRE protocols using a 3-wire interface (SCLK, CNVST, DOUT). It operates in all four SPI modes (CPOL/CPHA combinations). Each conversion yields a 16-cycle frame: three leading zeros, ten data bits (MSB first), two sub-bits (S1, S0), and one trailing zero. DOUT transitions tDOUT after each SCLK rising edge and remains valid for tDHOLD (4 ns) afterward.

What is the analog input structure of the MAX1071ETC, and how does it differ from the MAX1070ETC?

The MAX1071ETC features a true-differential analog input with bipolar range (–VREF/2 to +VREF/2), implemented via an internal switched-capacitor T/H and SAR core. In contrast, the MAX1070ETC has a unipolar input (0 to VREF). Both share identical pinout, timing, power, and interface behavior - differing only in transfer function (two's complement for MAX1071ETC vs. straight binary for MAX1070ETC) and input voltage range definition.